CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of priority to U.S. Application Serial No. 62/935,400, filed on November 14, 2019. The content of U.S. Application Serial No. 62/935,400 is considered part of the disclosure of the present document and is incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

[0002] This document describes devices, systems, and methods related to electrode arrays for sensing and/or stimulating a brain of a mammal (e.g., a human) or other animal.

2. Background Information

[0003] Electroencephalography (EEG) is a method for sensing the electrical activity within the brain. EEG can be noninvasive where electrodes are placed on the scalp, or it can be invasive where the electrodes are placed directly on the brain. Some electrodes are placed on the surface of the scalp or brain (i.e. cortex), while other probes penetrate into the brain tissue. EEG is used to detect and diagnose a variety of ailments, including epilepsy, encephalitis, stroke, sleep disorders, and dementia.

[0004] Beyond clinical diagnosis and treatment, there is growing interest in brain- machine interfaces whereby the brain is able to interact with external machines such as computers. Both noninvasive and invasive electrodes are showing promise of enabling human thought to control external systems and conversely external systems to influence human thought. Electrodes that make electrical contact with the brain are required to enable the brain-machine interface.

SUMMARY

[0005] Some embodiments described herein include an electroencephalography (EEG) electrode system for sensing and/or stimulating a brain while reducing risk associated with the sensing and stimulation. In some implementations, the electrode system can be an electroencephalography (EEG) electrode system. In other implementations, the same electrode system can be used in non-EEG applications, such as within a brain-machine interface. The system is scalable to different numbers of contacts to span large areas of the brain. For example, the system includes an EEG electrode array made with a plurality of patches connected together physically and electrically. In some implementations, each patch can have its own respective intelligent multiplexer and/or intelligent demultiplexer to aggregate the respective sense and/or stimulate signals. Alternatively or in addition, the electrode array can include an application-wide intelligent multiplexer and/or intelligent demultiplexer to subsequently aggregate the signals for each patch, thereby reducing the wire or lead count down to a single wire or wireless link. In some implementations, each patch, or the array as a whole, can have an embedded ground plane, thus minimizing the susceptibility to external electromagnetic (EM) noise or interference. Moreover, the physical resolution of each patch, or the array at a whole, can be adjusted as needed.

[0006] Particular embodiments described herein include a brain electrode device including a plurality of contact points, a plurality of sub-circuits, and a plurality of sub circuits. The plurality of sub-circuits includes sensor ports configured to connect to the contact points, respectively. The plurality of sub-circuits is configured to aggregate signals from the plurality of sub-circuits and generate an aggregate signal. The aggregate signal may be transmitted to a signal acquisition device.

[0007] In some implementations, the system can optionally include one or more of the following features. The plurality of sub-circuits may include sample/hold circuits configured to sample respective input signals and hold its value. The brain electrode device may further include a snapshot signal circuit configured to instruct the sample/hold circuits with timings of sampling the input signals. The snapshot signal may be configured to reset the sample/hold circuits during a next snapshot pulse. The signal acquisition system may include an analog-to-digital converter and a digital signal processor.

[0008] Particular embodiments described herein include a method for sensing signals from a brain. The method may include one or more of the following processes: engaging an electrode array with the brain, the electrode array including a plurality of cells; sampling signals at the respective cells; aggregating, using an intelligent multiplexer, the signals; and transmitting an aggregated signal to a signal acquisition circuit for processing.

[0009] In some implementations, the system can optionally include one or more of the following features. The method may further includes holding the signals at the respective cells. The method may further include time-aligning the signals prior to aggregating the signals. The time-aligning the signals may include injecting a snapshot signal to the cells, the snapshot signal configured to control timings of sampling the signals at the respective cells. [0010] Particular embodiments described herein include a brain electrode device including a plurality of contact points, a plurality of sub-circuits, and an intelligent demultiplexer. The plurality of sub-circuits may include sensor ports configured to connect to the contact points, respectively. The intelligent demultiplexer may be configured to accept an input signal an aggregate of signals from a control device. The input signal may be an aggregate of signals. The intelligent demultiplexer may be configured to distribute the signals in the input signal to their respective destinations.

[0011] Particular embodiments described herein include a brain electrode device including a plurality of contact points, a plurality of sub-circuits, a plurality of adder circuits, and an intelligent multiplexer. The plurality of sub-circuits may include sensor ports configured to connect to the contact points, respectively. Each of the plurality of adder circuits may be configured to aggregate signals from a group of sub-circuits and generate an adder aggregate signal. The group may be selected from the plurality of sub-circuits. The intelligent multiplexer may be configured to aggregate signals directly from the plurality of sub-circuits, or aggregate the adder aggregate signals from the adder circuits. The intelligent multiplexer may be configured to generate an aggregate signal being transmitted to a signal acquisition device.

[0012] In some implementations, the system can optionally include one or more of the following features. The plurality of sub-circuits may include sample/hold circuits configured to sample respective input signals and hold its value. The brain electrode device may further include a snapshot signal circuit configured to instruct the sample/hold circuits with timings of sampling the input signals. The snapshot signal may be configured to reset the sample/hold circuits during a next snapshot pulse. The signal acquisition system may include an analog-to-digital converter and a digital signal processor.

[0013] Particular embodiments described herein include a method for sensing signals from a brain. The method may may include one or more of the following processes: engaging an electrode array with the brain, the electrode array including a plurality of cells and groups of cells being selected from the plurality of cells; sampling signals at the respective cells; aggregating, using each of a plurality of adder circuits, signals from each of the groups of cells to generate a first aggregate signal; aggregating, using an intelligent multiplexer, the first aggregate signals from the plurality of adder circuits to generate a second aggregate signal; and transmitting the second aggregate signal to a signal acquisition circuit for processing.

[0014] In some implementations, the system can optionally include one or more of the following features. The method may further include aggregating, using the intelligent multiplexer, the signals from the cells; and transmitting the aggregated signal to the signal acquisition circuit. The method may further include holding the signals at the respective cells. The method may further include time-aligning the signals prior to aggregating the signals. Time-aligning the signals may include injecting a snapshot signal to the cells, the snapshot signal configured to control timings of sampling the signals at the respective cells. [0015] Particular embodiments described herein include a brain electrode device including an electrode array membrane, a plurality of fine-resolution contact points, and a coarse-resolution contact point. The plurality of fine-resolution contact points may be distributed in an array across a surface of the electrode array membrane. The coarse- resolution contact point may include a perforated plate. The plate may have a plurality of holes within which the plurality of fine-resolution contact points are disposed.

[0016] Particular embodiments described herein include a brain electrode device including a sensing circuit and a stimulating circuit. The sensing circuit may include a plurality of first contact points, a plurality of first sub-circuits, and an intelligent multiplexer. The plurality of first sub-circuits may include sensor ports configured to connect to the first contact points, respectively. The intelligent multiplexer may be configured to aggregate signals from the plurality of first sub-circuits and generate an aggregate signal. The aggregate signal may be transmitted to a signal acquisition device. The stimulating circuit may include a plurality of second contact points, a plurality of second sub-circuits, and an intelligent demultiplexer. The plurality of second sub-circuits may include sensor ports configured to connect to the second contact points, respectively. The intelligent demultiplexer may be configured to receive a single stimulation signal from a controller and generate a plurality of sub-stimulation signals being transmitted to the plurality of second sub -circuits.

[0017] In some implementations, the system can optionally include one or more of the following features. The sensing and the stimulating circuit may be operated independently. The sensing circuit and the simulating circuit may be simultaneously operated. The plurality of sub-circuits may include sample/hold circuits configured to sample an input signal and hold its value. The brain electrode device may further include a snapshot signal circuit configured to transmit a snapshot signal to instruct the sample/hold circuits with timings of sampling the input signals. The snapshot signal may be configured to reset the sample/hold circuits during a next snapshot pulse. The signal acquisition system may include an analog- to-digital converter and a digital signal processor.

[0018] Particular embodiments described herein include a method for sensing signals from a brain and stimulating the brain. The method may include one or more of the following processes: engaging an electrode array with the brain, the electrode array including a plurality of cells; sensing signals from the brain by sampling signals at the respective cells; aggregating, using an intelligent multiplexer, the signals; and transmitting an aggregated signal to a signal acquisition circuit for processing; stimulating the brain by obtaining a stimulation signal; generating, using an intelligent demultiplexer, a plurality of sub stimulation signals from the stimulation signal; and transmitting the plurality of sub stimulation signals to the plurality of cells. Sensing the signals from the brain may be performed simultaneously with stimulating the brain. Sensing the signals from the brain may further include holding the signals at the respective cells. Sensing the signals from the brain may further include time-aligning the signals prior to aggregating the signals. Time-aligning the signals may include injecting a snapshot signal to the cells, the snapshot signal configured to control timings of sampling the signals at the respective cells.

[0019] Particular embodiments described herein include a brain electrode device including a plurality of patches, and an intelligent multiplexer. The plurality of patches may be movably connected in array. Each patch may include a plurality of contact points, and a sub-circuit including a sensor port configured to connect to the contact points. The intelligent multiplexer may be configured to aggregate patch signals from the plurality of contact points into an aggregate signal. The aggregate signal may be transmitted to a signal acquisition device.

[0020] In some implementations, the system can optionally include one or more of the following features. Each patch may include a tab and a slot configured to receive a tab from an adjoining patch. Each patch may include a plurality of tabs at an end and a plurality of slots at another end and configured to receive a plurality of tabs from an adjoining patch. The tabs of the patch are attached to the adjoining patch using adhesive. The tabs of the patch may be attached to the adjoining patch using a fastener. Each path may include a patch multiplexer configured to aggregate signals from the sub-circuit in the patch and generate a patch signal. The tabs may be flexible. The tabs may include electronics thereon and are configured to isolate the electronics from a brain tissue to which the plurality of patches is engaged. The electronics may include the intelligent multiplexer. The brain electrode device may further include marks provided on the tabs and configured to measure an effective insertion distance of the tabs.

[0021] Particular embodiments described herein include a brain electrode device including a plurality of contact points, a plurality of sub-circuits, a ground electrode wire, and a signal electrode wire. The plurality of sub-circuits may include sensor ports configured to connect to the contact points, respectively. The signal electrode wire may be routed parallel with the ground electrode wire and spaced apart from the ground electrode wire at a predetermined distance.

[0022] In some implementations, the system can optionally include one or more of the following features. The predetermined distance may range between 1 micron and 10 millimeters. The brain electrode device may further include an intelligent multiplexer configured to aggregate signals from the plurality of sub-circuits and generate an aggregate signal. The aggregate signal may be transmitted to a signal acquisition device. The plurality of sub-circuits may include sample/hold circuits configured to sample an input signal and hold its value. The brain electrode device may further include a snapshot signal circuit configured to transmit a snapshot signal to instruct the sample/hold circuits with timings of sampling the input signals. The snapshot signal may be configured to reset the sample/hold circuits during a next snapshot pulse. The signal acquisition system may include an analog- to-digital converter and a digital signal processor.

[0023] The devices, system, and techniques described herein may provide one or more of the following advantages. Some embodiments described herein include EEG electrode arrays with an intelligent multiplexer for aggregating signals from multiple contact points, thereby reducing the wire count between the electrode array and an external signal acquisition system, and further reducing the extent of the external acquisition system, thus enabling massive scaling of the quantity of contact points.

[0024] Also, some embodiments of the EEG electrode arrays include intelligent multiplexers or intelligent demultiplexers that enable real-time sub-sampling or sub- stimulation, respectively, of the available contacts to control the amount of available data or vary the effective contact density within specific regions of the brain.

[0025] Further, some embodiments of the EEG electrode arrays disclosed herein are configured to adapt their physical resolution from wide pitch (for identifying the general area of interest) to fine pitch (for pinpointing the location for treatment) in such a way to eliminate the need to physically replace electrode arrays and thus reduce risk to the patient.

[0026] Addition, some embodiments of the EEG electrode arrays enable multiple contacts to be electrically tied together to reduce the effective contact resistance between the contacts and the brain, thereby improving the resulting signal quality.

[0027] Moreover, some embodiments of the EEG electrode arrays disclosed herein provide the ability to both sense and stimulate signals with one electrode array, thereby reducing risk to the patient simply due to the elimination of need to apply/remove/reapply electrodes for the different purposes. In addition, such arrays can further provide the ability to perform real-time, closed-loop treatment to patients so that the patient’s condition can be continually monitored (sensed) during treatment (stimulated), which enables more precise and safer treatment.

[0028] In addition, some embodiments disclosed herein include EEG electrode arrays having multiple patches configured to conform to the brain’s three-dimensional shape without degradation of contact resistance or harm to the patient. These same patches can be tacked together to ensure they stay physically stable relative to one another, thus improving repeatability between different applications of the electrode arrays.

[0029] Further, some embodiments of EEG electrode arrays have ground planes within and between patches to increase immunity to external EM noise, thus improving the quality of electrical signal and patient care.

[0030] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] FIG. 1 illustrates an example system with an EEG electrode array that can cover an outer surface of the brain.

[0032] FIG. 2 illustrates a circuit diagram of an example EEG electrode array circuit. [0033] FIG. 3 is a flowchart of an example process for acquiring signals from a brain using an electrode array.

[0034] FIG. 4 illustrates an example EEG electrode array.

[0035] FIG. 5 is a flowchart of an example process for acquiring signals from a brain using an electrode array.

[0036] FIG. 6 illustrates a zoomed-in view of contact points on an electrode array membrane.

[0037] FIG. 7 illustrates a diagram of an example EEG electrode array circuit for enabling sensing and stimulation through the same electrode array.

[0038] FIG. 8 illustrates an example structure of an EEG electrode array membrane for enabling simultaneous sensing and stimulating.

[0039] FIG. 9 is a flowchart of an example process for sensing and stimulating a brain using an electrode array.

[0040] FIG. 10 illustrates an example EEG electrode array membrane constructed with a plurality of patches to provide consistent and sufficient contact pressure across all contact points.

[0041] FIG. 11A illustrates an example configuration of electrodes that are highly susceptible to EM noise.

[0042] FIG. 1 IB illustrates an example configuration of electrodes for reducing noise susceptibility in EEG electrodes.

[0043] FIG. 12 is a block diagram of computing devices that may be used to implement the systems and methods described in this document.

DETAILED DESCRIPTION

[0044] Referring to FIG. 1, an example system 100 is described which includes an EEG electrode array 102 that can cover an outer surface of the brain (or cortex). As described herein, the EEG electrode array 102 can be modular and easily adapted to different shapes and sizes, such as a size that covers the entire outer surface of the brain’s cortex or a size that covers a smaller region of the surface of the brain. In some implementations, the EEG electrode array 102 can be made with a plurality of patches 104 which may be connected together physically (e.g., mechanically), electrically, or both. As described in more detail with reference to FIG. 10, the patches 104 can be connected through tabs and slots (e.g., one or more tabs on each of a plurality of sides, and one or more slots on each of the other plurality of sides).

[0045] In some implementations, each patch 104 has its own respective circuitry for an intelligent multiplexer (as described in FIGS. 2-6) and/or intelligent demultiplexer (as described in FIGS. 7-9) to aggregate the respective sense and/or stimulate signals. In addition or alternatively, the electrode array 102 can include circuitry for an application-wide intelligent multiplexer (as described in FIGS. 2-6) and/or intelligent demultiplexer (as described in FIGS. 7-9) to subsequently aggregate the signals for each patch, thereby reducing the wire count down to a single wire or wireless link.

[0046] In some implementations, each patch 104 has an embedded ground plane (not shown) (as described in FIG. 11) that can be interconnected to the ground planes in the surrounding patches through the tabs, thus minimizing the susceptibility to external EM noise.

[0047] Each patch can have both sensing and stimulation capabilities, and the physical resolution can be adjusted as needed, as described in FIGS. 4-6.

[0048] The system 100 can further include a controller 110 for controlling the EEG electrode array 102. The controller 110 can provide several modules or circuits, such as a signal acquisition circuit 112 for acquiring an aggregate signal from the array 102, a stimulation circuit 114 for transmitting a stimulation signal to all or some of the patches 104 in the array 102, a resolution adjustment circuit 116 for adjusting sensing/stimulating resolutions of the array 102 (e.g., between wide pitch and fine pitch or sub-sample some of the available contact points), and a signal processor 118 for processing signals acquired from, and transmitted to, the array 102. In some implementations, the controller 110 can be connected to a remote computing device or server 130 via a network 120. The remote computing device or server 130 can receive data from the controller 110 for further analysis, management, storage, and transmission of data to the controller 110 for controlling and managing the controller 110 and the array 102 connected to the controller 110.

EEG Electrode Circuit with Intelligent Multiplexer and Sample/Hold [0049] FIG. 2 illustrates a circuit diagram of an example EEG electrode array circuit 200. In some embodiments, through use of a multiplexer, the electrode array circuit 200 can reduce the quantity of wires between the electrode array’s contact points and an external acquisition system.

[0050] In general, an example EEG apparatus may include electrodes that make electrical contact with a scalp or brain. For example, such electrodes can have single contact points, and each single-point electrode can have a respective discrete wire to an external signal acquisition system. In another example, an EEG apparatus may include electrodes that have arrays of contact points that are patterned across the surface of a flexible membrane. Such electrode arrays may use metal disks for the contacts. The metal is a good electrical conductor, and the physical thickness of the disk protrudes outward from the substrate’s surface to reduce the electrical contact resistance. From each disk, a wire is routed on the surface of or within the electrode array to a connector along the electrode’s edge, which is subsequently used to connect to an external signal acquisition system.

[0051] In yet another example, an EEG apparatus may be configured to attach a dedicated wire between each of the contact points and the external signal acquisition system. By doing so, each contact point can be independently and simultaneously acquired. However, this method constrains scalability due to the physical size and weight of the wires and due to the cost of the equipment needed to acquire each of the signals independently. For example, a high density electrode array may include 256 contacts (e.g., arranged as a 16 by 16 array).

The corresponding 256 copper wires of such an array can physically weigh multiple kilograms (pounds) and have an aggregate diameter of approximately 5 cm (2 inch). The massive bundle of wires can be cumbersome and severely limit patient mobility, can pose physical risks to the patient, and can preclude peripheral access to and treatment of the brain. [0052] The signal acquisition equipment may also be comparably expensive. After the basic framework is in place, each contact point within the electrode array requires a corresponding copper wire, connector, analog to digital converter (ADC), and signal processor. Roughly speaking, doubling the quantity of contact points approximately doubles the cost of the acquisition equipment.

[0053] The EEG electrode array circuit 200, and other circuits, device, and systems described herein, may at least partially mitigate one or more of these problems by reducing the wire count between the electrode array and an external signal acquisition system, and further reducing the extent of the external acquisition system, thus enabling massive scaling of the quantity of contact points without a corresponding increase in the number of wires or leads running between the electrode array circuit 200 and external acquisition system.

[0054] Referring to FIG. 2, the EEG electrode array circuit 200 includes multiple sub circuits 202 arranged in rows and columns. Each sub-circuit 202 corresponds to a different electrode contact (e.g., metal disc). The EEG electrode array circuit 200 includes circuitry for a multiplexer 210 to aggregate signals onto a common wire. As described herein, the intelligent multiplexer 210 can improve performance in multiple ways.

[0055] In general, a multiplexer is a circuit that accepts analog signals from multiple sources and combines them in an aggregated signal. The signals are combined in a manner that allows the individual input signals to be recovered by a de-multiplexer. For example, in a time-division scheme, the multiplexer may allow just one input signal to pass through to the output at a time. In effect, such a multiplexer acts as a single pole, multi-throw switch. The multiplexer 210 can be an intelligent multiplexer (iMux), which can be configured to follow one of several specific patterns. For example, the intelligent multiplexer 210 can sample across the top row of electrode contact points, and then subsequently sample the next row of points, and so forth. As an alternative example, the intelligent multiplexer 210 can sample every-Nth contact point to reduce the quantity of samples by a factor of N while effectively sensing across the full area of the electrode array. In an addition example, the intelligent multiplexer 210 can sample the first M rows and O columns of contact points to maintain maximum physical resolution in a sub-region of the electrode array. In an alternative implementation, the multiplexer 210 may be a digital multiplexer.

[0056] Because sequential sampling across a large number of contact points can introduce meaningful time differentials between the times when electrical activity of the brain is measured at different points, the electrode array circuit 200 can alternatively be configured to sample an electrical characteristic (e.g., a voltage, current, or resistance) of all or a subset of the contact points of the array 200 at substantially the same time (simultaneously).

[0057] Referring still to FIG. 2, the EEG electrode array circuit 200 includes a sensor port 220 and a sample/hold circuit 230 in each sub-circuit 202. The electrode’s contact points are connected to their respective sensor ports 220. At each sensor port 220, the sample/hold circuit 230 is provided which samples an input signal representing local electrical activity of the brain, and holds the sampled value until reset. In some implementations, to time-align the sampling, a common snapshot signal 250 is distributed to all or some of the sample/hold circuits 230. The snapshot signal 250 activates the sample/hold circuits 230 causing them to sample their respective signals (e.g., by sampling a voltage, resistance, or current value measured by the corresponding electrode contact point for the particular sample/hold circuit 230). The sampled value can be an analog value or digital value. In addition, the snapshot signal 250 can effectively reset the sample/hold circuits 230 during a next snapshot pulse. Through the use of the snapshot signal and corresponding sample/hold circuits, the signals across the entire EEG electrode array circuit 200 can be simultaneously captured.

[0058] After the measurements are captured, the intelligent multiplexer 210 sequentially retrieves the sampled values from each of the sample/hold circuits 230 corresponding to each contact point. The selected signal measurement is then forwarded to a signal acquisition system 240. An example of the signal acquisition system 240 includes an analog-to-digital converter (ADC) and a digital signal processor (DSP). The signal acquisition system 240 can be placed external to the patient.

[0059] In some implementations, each sub-circuit 202 (e.g., cell) of the array 200 can include local signal-conditioning circuits, such as amplifiers, filters, and integrators, as illustrated in FIG. 2.

[0060] As described, a single intelligent multiplexer 210 can service numerous contact points such that all corresponding signals are presented to the external acquisition system 240 through a single wire or wireless link. Further, the array 200 can be scaled up to cover a large array of contact points. By way of example, it is feasible to sample more than 100,000 contacts with the array 200 and aggregate those signals down to a single signal that is transmitted externally from the patient. In addition, the scalability can further increase by providing and grouping multiple intelligent multiplexers together.

[0061] In some implementations, the array 200 (e.g., the multiplexer 210) can be connected to the signal acquisition system 240 for a single, common wired transmission. In other implementations, a wireless connection, such as a radio link or optical link, can be used to connect the multiplexer 210 to the signal acquisition system 240.

[0062] In addition to reducing the wire count to the external acquisition equipment 240, the array 200 enables simplifying the equipment 240. Instead of having hundreds of connectors, ADCs, and DSPs for respective contact points, the signal acquisition equipment 240 can be reduced to a single connector, single ADC, and single DSP, as illustrated in FIG. 2. Further, the configuration of the array 200, which employs the intelligent multiplexer 210 and the sample/hold circuits 230, can significantly reduce the wire count, thereby also reducing risk to the patient, enabling patient mobility, and enabling massive scaling in the quantity of contact points.

[0063] FIG. 3 is a flowchart of an example process 300 for acquiring signals from a brain using an electrode array. For example, the process 300 can be performed using the EEG electrode array circuit 200 of FIG. 2. The process 300 can include engaging an electrode array (e.g., the EEG electrode array circuit 200) with contact points on a brain (Block 310). The process 300 can include sampling and holding input signals at respective cells (e.g., respective sub-circuits 202) (Block 312). In some implementations, the sampling can be time-aligned by distributing a signal (e.g., the snapshot signal 250) throughout all or some of the cells (e.g., the sub-circuits 202) (Block 320). The distributed signal is used to control the respective cells (e.g., the sample/hold circuits 230 therein) to instruct the cells on when to sample their respective input signals (measurements). In some implementations, the distributed signal causes each of the cells to capture their respective measurements at substantially the same time.

[0064] The process 300 can include aggregating the signals sampled at the respective cells (Block 314). For example, a multiplexer (e.g., the intelligent multiplexer 210) can be connected to the cells and operated to aggregate the signals from the cells. The process 300 can include transmitting the aggregated signal to a signal acquisition circuit (e.g., the signal acquisition system or equipment 240) which operates to acquire and process the aggregated signal for subsequent use.

EEG Electrode Array with Multi-Resolution Contacts [0065] Typical EEG electrode arrays may be limited in terms of a physical resolution of their contact points. An example of such typical EEG electrode arrays includes an array of contacts placed on a flexible membrane, where the contacts are approximately 1 mm in diameter and placed on a 1 cm pitch. Such a physically-large pitch may be useful in identifying a generalized region of a brain of interest, but the pitch can be too large to pinpoint the location of electrical anomalies for therapeutic purposes.

[0066] Some electrode arrays provide finer contact-pitches, which may enable clinicians to pinpoint the location of electrical anomalies for treatment. However, such probes can only cover a relatively-small region of the brain, and thus require prior use of larger-pitch electrodes and/or equipment to identify the general region of interest.

[0067] Further, the use of fixed-pitch electrode arrays may limit the accuracy and thus the quality of care. Moreover, fixed-pitch electrode arrays require the use of multiple electrode arrays at the risk of harming the patient from the application/removal/re-application process. [0068] As described herein, some example EEG electrode arrays described herein provide a single electrode array that can adapt its physical resolution from wide pitch (for identifying the general area of interest) to fine pitch (for pinpointing the location for treatment).

[0069] An alternative way to gain the most insight into the brain’s operation may be to cover the entire brain with contact points that are spaced at the finest-possible spatial resolution. However, there are several technological limits of typical electrode arrays that often preclude such an arrangement (as described above). Further, such an alternative method may not be cost-efficient due in part to complexity of signal acquisition equipment that would be required to acquire and process signals from the electrode array. For example, typical electrodes require each contact point to be individually and independently acquired and, therefore, the cost of the acquisition scales linearly with the quantity of contact points.

By way of example, doubling the quantity of contact points approximately doubles the cost of the acquisition equipment. If scaled to cover the entire brain as sub -millimeter spatial resolution, the cost of the acquisition equipment is unaffordable. Another practical limitation of using the alternative method relates to ability to process and use all the data. Even if a user could afford such complex acquisition equipment, the amount of data available from such a full-scale electrode array may be beyond the processing capability of commodity computers. [0070] Some implementations of EEG electrode arrays described herein can provide a multi-resolution array, without imposing any of the potential limitations described above.

For example, such EEG electrode arrays include a coars e-resolution array that can cover the entire, or a large part of, a brain, and enable clinicians to identify a general area within the brain where an interesting activity is occurring. The coarse resolution can enable extensive or full spatial coverage of the brain while limiting the complexity/cost of the associated acquisition equipment and data-processing computer.

[0071] After the general area-of-interest of the brain is identified, the EEG electrode array 400 can change the spatial resolution to a much finer pitch. While doing so, the quantity of contact points can be held constant, thus the effective bandwidth of data to be acquired and processed can be held constant, thus making the overall system affordable and obtainable.

[0072] Referring to FIG. 4, an example EEG electrode array 400 is configured and operated similarly to the EEG electrode array circuit 200 above, such as including an intelligent multiplexer 410, sensor ports 420, sample/hold circuits 430, a signal acquisition system 440, a snapshot signal line 450, which are similar to the intelligent multiplexer 210, the sensor ports 220, the sample/hold circuits 230, the signal acquisition system 240, and the snapshot signal line 250, respectively. In addition, the EEG electrode array 400 is configured to provide multi-resolution arrays. For example, the array 400 is configured to aggregate the signals into “groupings” of contact points using adders. The size and shape of the localized regions can be modified to meet a particular need, but regardless the circuit is configured to sum and/or average the signals from multiple contact points to generate an aggregated measurement/signal, and present the aggregate measurement/signal to the user.

[0073] As a descriptive example, the EEG electrode array 400 can include contact points on a very-fine 0.1 mm pitch, thus enabling 0.1 mm spatial resolution. Each contact point could be connected to the intelligent multiplexer (iMux) 410, thus enabling each and every contact point to be independently sampled. In addition, each contact point within a certain region of the array (e.g., 10 x 10 sub-array) can be connected to a local adder circuit 460, where all the collection of 100 signals are summed/averaged, and the aggregate signal is connected to the iMux 410. Through proper control of the iMux 410, the user can then be presented with the signals from each individual contact point when fine spatial resolution (e.g. , 0.1 mm) is needed, or the user could be presented with just the aggregate signals when course spatial resolution (e.g., 1 mm) is better suited.

[0074] As such, the EEG electrode array 400 can provide additional benefits. For example, by summing the voltages from across the contact points, the resulting signal will suppress the noise simply through mathematical averaging of the contact points. Further, the effective contact resistance between the contacts and the brain can be reduced due to the parallel connections of the multiple contacts. These benefits can further improve the resulting signal quality.

[0075] FIG. 5 is a flowchart of an example process 500 for acquiring signals from a brain using an electrode array. For example, the process 500 can be performed using the EEG electrode array 400 of FIG. 4. The process 500 can include engaging an electrode array (e.g., the EEG electrode array 400) with contact points in a brain (Block 510). The process 500 can include sampling and holding input signals at respective cells (e.g., respective sub-circuits 402) (Block 512). In some implementations, the sampling can be time-aligned by distributing a signal (e.g., the snapshot signal 450) throughout all or some of the cells (e.g., the sub-circuits 402) (Block 520). The distributed signal is used to control the respective cells (e.g., the sample/hold circuits 430 therein) to instruct the cells on when to sample their respective input signals.

[0076] In some implementations, the cells (e.g., the sub-circuits 402) that correspond to respective contact points can be grouped to cover larger regions (e.g., cell groups 404 in FIG. 4) which correspond to respective groups of cells or contact points. The process 500 can include aggregating signals from respective groups of cells (Block 514). For example, for each cell group 404, the signals from the respective cells are aggregated (e.g., collected, summed, averaged, etc.) to generate a first aggregate signal.

[0077] The process 500 can include aggregating the first aggregate signals from the respective cell groups to generate a second aggregate signal (Block 516). For example, a multiplexer (e.g., the intelligent multiplexer 410) can be connected to the cell groups and operated to aggregate the first aggregate signals from the cell groups. The process 500 can include transmitting the second aggregate signal to a signal acquisition circuit (e.g., the signal acquisition system or equipment 440) which operates to acquire and process the signal for subsequent use.

[0078] Referring to FIG. 6, an example structure of an EEG electrode array membrane 600 is illustrated for providing multi-resolution contact points. The EEG electrode array membrane 600. FIG. 6 illustrates a zoomed-in view of contact points 670 (including 680 and 690) on the surface 672 of the electrode array membrane 600. A plurality of fine-resolution contact points 680 are distributed in a regular array across the surface 672 of the electrode array membrane 600. In addition, the electrode array membrane 600 includes perforated plates 690 surrounding the fine-resolution contact points 680. For example, each plate 690 includes a plurality of holes 692, and the fine-resolution contact points 680 are disposed within the respective holes 692. The plates 690 can act as coarse-resolution contact points themselves. As the shapes of the plates 690 are physically larger, they can provide larger spatial resolution and better contact resistance. All contact points - including the discrete/small ones (i.e., the fine-resolution contact points 680) and the larger ones (i.e., the coarse-resolution contact points 690) - are presented to an intelligent multiplexer (similar to the iMux 210 or 410), and thus they can be selected as needed to obtain a measurement for selectively larger or smaller areas of the brain.

[0079] As such, the array circuit 400 and array membrane 600 can provide multiple spatial resolutions within a single electrode array, thereby reducing risk to the patient, expediting diagnoses and treatment, and improving accuracy of treatment.

EEG Electrode Array with Simultaneous Sense and Stimulation [0080] Typical EEG electrode arrays are limited to sensing (acquiring) signals from the brain, and cannot be used for stimulating or treatment of the brain. In practice, EEG electrode arrays are first placed on the scalp or brain to diagnose the ailment and pinpoint the tissue of interest. The electrode array and associated equipment are then physically removed from the patient. Separate equipment is then brought in to treat the tissue, after which the stimulation equipment is removed, and the EEG electrode array is often then re-applied to measure the effectiveness of the treatment. The act of removing and re-applying electrodes poses risk to the patient. It also constrains treatment to open-loop techniques, which degrades accuracy and effectiveness of the treatment.

[0081] Some implementations of EEG electrode arrays described herein are configured to provide treatment therapies through electrical stimulation (e.g., electroconvulsive therapy, vagus nerve stimulation [VNS], and deep brain stimulation [DBS]) while simultaneously sensing the brain’s activities.

[0082] FIG. 7 illustrates a diagram of an example EEG electrode array circuit 700 for enabling sensing and stimulation through the same electrode array. The EEG electrode array circuit 700 may be configured similarly to the array circuits 200, 400. For example, the EEG electrode array circuit 700 includes sensing circuitry similar to at least part of the array circuits 200, 400, such as including an intelligent multiplexer 710, sensor ports 720, sample/hold circuits 730, a signal acquisition system 740, a snapshot signal line, which are similar to the intelligent multiplexer 210, 410, the sensor ports 220, 420, the sample/hold circuits 230, 430, the signal acquisition system 240, 440, and the snapshot signal line 250, 450, respectively. [0083] In addition to (or in parallel with) the sensing circuitry, the EEG electrode array circuit 700 includes an intelligent demultiplexer (iDemux) 760 configured to inject electrical signals into the contact points (through stimulation electrodes 762). In the illustrated example, the sensing and stimulating contact points are configured as separate entities. However, in other examples, the electrical circuit can be designed to enable common contact points to be shared for both sensing and stimulating. The EEG electrode array circuit 700 can further include a controller 764 for controlling the demultiplexer 760. The controller 764 may be connected to the demultiplexer 760 via other signal conditioning elements, such as a digital-to-analog converter 766 (DAC) to produce an analog signal that is further modified bysignal-conditioning circuits 770, such as amplifiers, filters, and integrators, as illustrated in FIG. 7.

[0084] In one embodiment of the EEG electrode array circuit 700, the sensing circuits (including 730, 710, 740) are actively sensing the patient while the stimulation circuits (including 770, 760, 766, 764) are inactive. By doing so, the stimulation circuits (including 770, 760, 766, 764) are not inadvertently creating EM signals that are couple into the brain or the sensing circuits (including 730, 710, 740), thus improving the quality of the sensed signals.

[0085] Alternatively, the EEG electrode array circuit 700 can be configured to inactivate the sensing circuits (including 730, 710, 740) and activate stimulation circuits (including 770, 760, 766, 764) to stimulate the patient’s brain. In this configuration, the stimulated signals are applied to the patient.

[0086] Also, the EEG electrode array circuit 700 can be configured to simultaneously activate both the sensing circuits (including 730, 710, 740) and stimulation circuits (including 770, 760, 766, 764). In this configuration, the sensing circuits (including 730, 710, 740) can be used to either: 1) measure the applied signals from the stimulation circuits (including 770, 760, 766, 764); or 2) measure the patient’s response to the applied signals. Of particular interest, applying a feedback path 780 between the signal acquisition system 740 and the controller 764, the sensed signal can be used to calibrate and adjust the strength and characteristics of the stimulation signal, thus improving clinical effectiveness and reducing risk to the patient.

While the EEG electrode array circuit 700 is generating stimulation signals, the intelligent demultiplexer 760 enables a wide range of options, such as: 1) it can send the same signal to all contact points 762, thus stimulating large sections of the brain; 2) it can selectively send the same signal to a user-defined subset of contact points 762, thus stimulating smaller sections of the brain; 3) it can selectively send different signals to each contact point 762, thus effectively stimulating the brain with a three-dimensional waveform (X, Y, and time); or 4) it can send a signal to a user-selected single contact point 762, thus enabling precise application of stimulation signals.

[0087] Referring to FIG. 8, an example structure of an EEG electrode array membrane 800 is illustrated for enabling simultaneous sensing and stimulating. The array membrane 800 is configured to leverage the example structure of the array 600 as depicted in FIG. 6.

The array membrane 800 includes a substrate 802 that includes sensing contact points 810 and stimulating contact points 820 which are electrically isolated from one another. For example, the sensing contact points 810 are interspersed within the stimulating contact points 820. Each stimulating contact point 820 can include a plurality of holes 822, and the sensing contact points 810 are disposed within the respective holes 822. In this particular example, the stimulating contact points 820 are physically larger and surrounding the sensing contact points 810, but other configurations can be designed.

[0088] As such, the array circuit 700 and membrane 800 provides the ability to sense and stimulate signals with one electrode array, thereby reducing risk to the patient simply due to the elimination of need to apply/remove/reapply electrodes for the different purposes. In addition, the array circuit 700 and membrane 800 can further provide the ability to perform real-time, closed-loop treatment to patients. That is, the patient’s condition can be continually monitored (sensed) during treatment (stimulated), which enables more precise and safer treatment.

[0089] FIG. 9 is a flowchart of an example process 900 for sensing and stimulating a brain using an electrode array. For example, the process 900 can be performed using the EEG electrode array circuit 700 and membrane 800 of FIGS. 7 and 8. The process 900 can include engaging an electrode array (e.g., the EEG electrode array circuit 700, 800) with contact points in a brain (Block 910). The process 900 can include determining whether the electrode array is in a sensing mode or a stimulating mode (Block 912). If it is in a sensing mode, the process continues on by performing a sensing operation (Block 914). Example sensing operations can be described as the processes 300 (FIG. 3) and 500 (FIG. 5). Other processes are also possible for the sensing operation. [0090] If the electrode array is determined to be in a stimulating operation, the process includes a stimulating operation (Block 916). For example, the stimulating operation can be performed by generating a control signal (Block 920), transmitting the control signal to a demultiplexer (e.g., the intelligent demultiplexer described herein) to generate multiple sub control signals (Block 922), and transmitting the sub-control signals to the cells for local stimulation (Block 924).

EEG Electrode Array with Conforming Shape [0091] Electrode arrays may be typically fabricated in simple rectangular patterns on flexible, non-elastic membranes. The flexibility enables the electrode to conform in one dimension of the brain’s curvature, but it limits the conformity in the other direction. By analogy, a common sheet of paper can be rolled in one direction, but if that same sheet of paper is forced to conform to the shape of a sphere (e.g., ball), the paper will crinkle and crease around the periphery. Such crinkles and creases in electrode arrays pose potential harm to the patient, and they separate the contact points from the brain, thus rendering those particular contacts useless.

[0092] Some implementations of EEG electrode arrays described herein are configured to conform to spherical-like objects, such as the brain, while maintaining consistent contact pressure without creating crinkles and creases. Further, the arrays are modular, enabling clinicians to create custom sized and shaped arrays based on the pattern of patches selected and applied.

[0093] Referring to FIG. 10, an example EEG electrode array membrane 1000 can be constructed with a plurality of patches 1002 to provide consistent and sufficient contact pressure across all contact points. The EEG electrode array membrane 1000 can be configured similarly to the arrays 200, 400, 700, for example. Two patches are depicted in FIG. 10, but more than two patches can be envisioned. In some implementations, each patch 1002 has one or more tabs 1010 at an end, and one or more slots 1012 at an opposite end.

The tabs 1010 from one patch 1002 can be inserted through the slots 1012 of an adjoining patch 1002. Although each patch 1002 is illustrated to have two tabs on one side of a square patch, but different shaped patches, quantity and placement of tabs, and quantity and placement of slots are envisioned to enable a wide range of configurations. [0094] The EEG electrode array membrane 1000 with patches can provide several advantageous configurations. For example, the array membrane 1000 can have graduated scales on them, thus enabling the physician to precisely record the relative insertion of each patch. With this information, the physician can numerically determine the shape of the overall array and can later replicate the placement and position of the patches.

[0095] Further, by recording the insertion of each tab, the physician can precisely recreate the same aggregate shape and pattern of the electrode array. That is, the insertion lengths of each tab will enable physicians to create a computer aided design (CAD) model of the three- dimensional (3D) shape of the overall electrode array and thus of the brain’s outer surface. [0096] The tabs enable the patches to be bonded to one another. With the use of adhesives or fasteners, the tabs from one patch can be held in constant position on the adjacent patch. By doing, the relative position of the overall electrode array will remain constant.

[0097] Correspondingly, the overall electrode array can be physically removed from the patient, all the while the overall electrode array retaining its geometrical shape. If needed, the tabs then allow the electrode array to be reapplied to the patient in the precise location where it was originally placed. Finally, the tabs can also provide electrical connectivity between patches. As discussed a bit later, providing electrical connectivity between patches will improve signal quality/fidelity.

[0098] The tabs can provide a convenient location to place the electronics, such as the iMux described earlier. In particular, a tab with the iMux could be bent outward from the brain, thus thermally isolating the heat generated by the iMux from harming the brain.

[0099] Similarly, the same or different tab can be used to connect to the external acquisition equipment or host the iDemux.

[0100] To further aid in generating a 3D CAD model of the array, the tabs and/or the patch itself can have identifying marks on them. For example, each tab can have a fiducial that identifies the physical location of that tab. Using Xray, CT, MR, visual, or other imaging techniques, the 3D location of the fiducials can be precisely identified and recorded.

[0101] Moreover, the patches enable a broad range of scalability. A single patch can be used to cover a small, specific area of the brain. Or, a collection of patches can be applied to cover the entire brain. In patch form, there’s no inherent limit to the quantity of patches or the physical area which they cover. [0102] In the illustrated embodiment in FIG. 10, the patches are configured as being discrete from one another. In other embodiments, all or some patches can be provided on a common substrate. In such embodiments (not shown), the tabs are at fixed locations on the patches, and they inter-stitch between the patches. To conform to the brain’s shape, the tabs are bent upward and crimped to shorten the physical distance between the patches, thus producing the same effect.

[0103] As described above, through the use of patches with tabs, the electrode array can conform to the brain’s three-dimensional shape without degradation of contact resistance or harm to the patient.

EEG Electrode Array with Ground Reference [0104] Typical EEG electrode arrays are configured to separate the “ground” contact from the other contacts. That is, the primary signals are acquired from contact points that are placed across the brain, and a separate contact point (i.e., most often with a large, single contact point) is located on a physically-separate location of the brain. This separate single contact electrode is designated as “ground,” and it is used as a voltage reference for all the other signals.

[0105] The physical separation of the ground contact degrades the quality of the detected signals. In brief, physical separation of the wires creates an electromagnetic (EM) environment that is susceptible to external EM noise. The external noise is generated from man-made emitters such as cell phones, fluorescent lighting, radio towers, and surrounding surgical equipment. And nature creates EM noise through variations in the earth’s magnetic fields.

[0106] The EM noise manifests itself in two general forms: common mode and differential mode. Common-mode noise has the effect of offsetting all signals by the same voltage amount relative to the “ground” contact. Differential-mode noise has the effect of offsetting the signals relative to one another. Common- and differential-mode noise cannot be completely shielded; it will affect the quality of all signals. However, typical methods of separating the ground contact increase the susceptibility to external noise and thus degrades performance.

[0107] Some implementations of EEG electrode arrays described herein provide a physical design that reduces the susceptibility to external EM noise. [0108] As described above, electrode arrays are susceptible to EM noise. Such EM noise comes from nature, man-made sources, and from themselves (i.e., crosstalk). The susceptibility to noise is directly dependent on the relative separation between the electrode’s “signal” contacts and the “ground” contact.

[0109] Referring to FIG. 11 A, an example configuration 1100 A of electrodes is illustrated, which are highly susceptible to EM noise. For example, a first electrode wire 1102 is designated as the “ground” contact or wire, and a second wire 1104 is designated as the “signal” contact or wire. Based on classical antenna theory, the amount of signal that an antenna receives is directly proportional to its aperture, and its aperture is approximated by the effective physical area between signal and ground wires. In the case of EEG electrodes, the reception is of EM noise, so the larger the area (i.e., larger the aperture) increases the electrode’s susceptibility to noise. As previously discussed, the ground electrode is often placed on the opposite side of the brain relative to the signal electrodes, which creates the largest-possible aperture and thus maximizes the noise susceptibility.

[0110] Referring to FIG. 1 IB, an example configuration 1100B of electrodes is illustrated for reducing noise susceptibility in EEG electrodes. For example, the electrode configuration 1100B is to reduce the aperture by reducing the separation between the signal wire 1104 and the ground wire 1102. In some implementations, the signal wire 1104 is at least partially routed substantially parallel with the ground wire 1102. The signal wire 1104 can be spaced apart from the ground wire 1102 at a distance ranging between 1 micron and 10 mm.

[0111] An approach of pairing each signal wire with a ground wire may double the wire count and the quantity of contact points. Further, by placing grounds across the brain’s entire surface, the electrical signals may effectively be shorted to one another, thus masking the signals from detection. Moreover, the ground wires themselves act as antennas, and the existence of numerous ground wires can inadvertently increase noise due the common-mode noise received through the grounds.

[0112] The configuration 1100B of electrodes, which minimizes the aperture, can use one common ground across the entire electrode array, where the sole ground contact is placed near the furthest distance away from the external acquisition equipment. In some implementations, the ground “wire” can be implemented as a planar sheet of metal, called a ground plane. The ground plane needs to be continuous across all or part of the electrode array substrate, or of all the patches as shown in FIG. 10 where the tabs provide connectivity between the patches. The ground plane can be placed immediately underneath each and every signal trace.

[0113] To provide the singular ground contact to the brain, a contact point within a standard electrode array can be used. In alternative embodiments, a custom electrode can be made that has a large, singular contact point.

[0114] As described above, through the use of ground planes within and between patches (as shown in FIG. 10), the electrode can be significantly immune to external EM noise, thus improving the quality of electrical signal and patient care.

Example Embodiments A - Electrode Circuit with Intelligent Multiplexer and Sample/Hold A1. A brain electrode device comprising: a plurality of contact points; a plurality of sub-circuits including sensor ports configured to connect to the contact points, respectively; and an intelligent multiplexer configured to aggregate signals from the plurality of sub circuits and generate an aggregate signal, wherein the aggregate signal is transmitted to a signal acquisition device.

A2. The brain electrode device of embodiment Al, wherein the plurality of sub-circuits includes sample/hold circuits configured to sample respective input signals and hold its value.

A3. The brain electrode device of embodiment A2, further comprising: a snapshot signal circuit configured to instruct the sample/hold circuits with timings of sampling the input signals.

A4. The brain electrode device of embodiment A3, wherein the snapshot signal is configured to reset the sample/hold circuits during a next snapshot pulse.

A5. The brain electrode device of any one of embodiments A1-A4, wherein the signal acquisition system includes an analog-to-digital converter and a digital signal processor.

A6. A method for sensing signals from a brain, comprising: engaging an electrode array with the brain, the electrode array including a plurality of cells; sampling signals at the respective cells; aggregating, using an intelligent multiplexer, the signals; and transmitting an aggregated signal to a signal acquisition circuit for processing.

A7. The method of embodiment A6, further comprising: holding the signals at the respective cells.

A8. The method of any one of embodiments A6-A7, further comprising: time-aligning the signals prior to aggregating the signals.

A9. The method of embodiment A7, wherein time-aligning the signals comprises: injecting a snapshot signal to the cells, the snapshot signal configured to control timings of sampling the signals at the respective cells.

Example Embodiment B - Electrode Circuit with Intelligent Demultiplexer B1. A brain electrode device comprising: a plurality of contact points; a plurality of sub-circuits including sensor ports configured to connect to the contact points, respectively; and an intelligent demultiplexer configured to accept an input signal an aggregate of signals from a control device, the input signal being an aggregate of signals, the intelligent demultiplexer configured to distribute the signals in the input signal to their respective destinations.

Example Embodiments C - Electrode Array with Multi-Resolution Contacts Cl . A brain electrode device comprising: a plurality of contact points; a plurality of sub-circuits including sensor ports configured to connect to the contact points, respectively; and a plurality of adder circuits, each adder circuit configured to aggregate signals from a group of sub-circuits and generate an adder aggregate signal, the group being selected from the plurality of sub-circuits; and an intelligent multiplexer configured to aggregate signals directly from the plurality of sub-circuits, or aggregate the adder aggregate signals from the adder circuits, the intelligent multiplexer configured to generate an aggregate signal being transmitted to a signal acquisition device.

C2. The brain electrode device of embodiment Cl, wherein the plurality of sub-circuits includes sample/hold circuits configured to sample respective input signals and hold its value.

C3. The brain electrode device of embodiment C2, further comprising: a snapshot signal circuit configured to instruct the sample/hold circuits with timings of sampling the input signals.

C4. The brain electrode device of embodiment C3, wherein the snapshot signal is configured to reset the sample/hold circuits during a next snapshot pulse.

C5. The brain electrode device of any one of embodiments C1-C4, wherein the signal acquisition system includes an analog-to-digital converter and a digital signal processor.

C6. A method for sensing signals from a brain, comprising: engaging an electrode array with the brain, the electrode array including a plurality of cells and groups of cells being selected from the plurality of cells; sampling signals at the respective cells; aggregating, using each of a plurality of adder circuits, signals from each of the groups of cells to generate a first aggregate signal; aggregating, using an intelligent multiplexer, the first aggregate signals from the plurality of adder circuits to generate a second aggregate signal; and transmitting the second aggregate signal to a signal acquisition circuit for processing. C7. The method of embodiment C6, further comprising: aggregating, using the intelligent multiplexer, the signals from the cells; and transmitting the aggregated signal to the signal acquisition circuit.

C8. The method of any one of embodiments C6-C7, further comprising: holding the signals at the respective cells.

C9. The method of any one of embodiments C6-C8, further comprising: time-aligning the signals prior to aggregating the signals.

CIO. The method of embodiment C7, wherein time-aligning the signals comprises: injecting a snapshot signal to the cells, the snapshot signal configured to control timings of sampling the signals at the respective cells.

C 11. A brain electrode device comprising: an electrode array membrane; a plurality of fine-resolution contact points distributed in an array across a surface of the electrode array membrane; and a coarse-resolution contact point including a perforated plate, the plate having a plurality of holes within which the plurality of fine-resolution contact points are disposed.

Example Embodiments D - Electrode Array with Simultaneous Sense and Stimulation

D1. A brain electrode device comprising: a sensing circuit including: a plurality of first contact points; a plurality of first sub-circuits including sensor ports configured to connect to the first contact points, respectively; and an intelligent multiplexer configured to aggregate signals from the plurality of first sub-circuits and generate an aggregate signal, wherein the aggregate signal is transmitted to a signal acquisition device; and a stimulating circuit including: a plurality of second contact points; a plurality of second sub-circuits including sensor ports configured to connect to the second contact points, respectively; and an intelligent demultiplexer configured to receive a single stimulation signal from a controller and generate a plurality of sub-stimulation signals being transmitted to the plurality of second sub-circuits.

D2. The brain electrode device of embodiment D1 , wherein the sensing and the stimulating circuit are operated independently.

D3. The brain electrode device of any one of embodiments D1-D2, wherein the sensing circuit and the simulating circuit are simultaneously operated.

D4. The brain electrode device of any one of embodiments D1-D3, wherein the plurality of sub-circuits includes sample/hold circuits configured to sample an input signal and hold its value.

D5. The brain electrode device of embodiment D4, further comprising: a snapshot signal circuit configured to transmit a snapshot signal to instruct the sample/hold circuits with timings of sampling the input signals.

D6. The brain electrode device of embodiment D5, wherein the snapshot signal is configured to reset the sample/hold circuits during a next snapshot pulse.

D7. The brain electrode device of any one of embodiments D1-D6, wherein the signal acquisition system includes an analog-to-digital converter and a digital signal processor.

D8. A method for sensing signals from a brain and stimulating the brain, comprising: engaging an electrode array with the brain, the electrode array including a plurality of cells; sensing signals from the brain by: sampling signals at the respective cells; aggregating, using an intelligent multiplexer, the signals; and transmitting an aggregated signal to a signal acquisition circuit for processing; and stimulating the brain by: obtaining a stimulation signal; generating, using an intelligent demultiplexer, a plurality of sub-stimulation signals from the stimulation signal; and transmitting the plurality of sub-stimulation signals to the plurality of cells.

D9. The method of embodiment D8, wherein sensing the signals from the brain is performed simultaneously with stimulating the brain.

DIO. The method of any one of embodiments D8-D9, wherein sensing the signals from the brain further comprises: holding the signals at the respective cells.

Dll . The method of any one of embodiments D8-D10, wherein sensing the signals from the brain further comprises time-aligning the signals prior to aggregating the signals.

D12. The method of embodiment D11 , wherein time-aligning the signals comprises: injecting a snapshot signal to the cells, the snapshot signal configured to control timings of sampling the signals at the respective cells.

Example Embodiments E Electrode Array with Conforming Shape

El . A brain electrode device comprising: a plurality of patches movably connected in array, each patch including: a plurality of contact points; and a sub-circuit including a sensor port configured to connect to the contact points; and an intelligent multiplexer configured to aggregate patch signals from the plurality of contact points into an aggregate signal, wherein the aggregate signal is transmitted to a signal acquisition device.

E2. The brain electrode device of embodiment El, wherein each patch comprises a tab and a slot configured to receive a tab from an adjoining patch.

E3. The brain electrode device of embodiment E2, wherein each patch comprises a plurality of tabs at an end and a plurality of slots at another end and configured to receive a plurality of tabs from an adjoining patch.

E4. The brain electrode device of embodiment E3, wherein the tabs of the patch are attached to the adjoining patch using adhesive.

E5. The brain electrode device of embodiment E3, wherein the tabs of the patch are attached to the adjoining patch using a fastener.

E6. The brain electrode device of any one of embodiments E1-E5, wherein each path includes: a patch multiplexer configured to aggregate signals from the sub-circuit in the patch and generate a patch signal.

E7. The brain electrode device of embodiment E3, wherein the tabs are flexible.

E8. The brain electrode device of embodiment E3, wherein the tabs include electronics thereon and are configured to isolate the electronics from a brain tissue to which the plurality of patches is engaged.

E9. The brain electrode device of embodiment E8, wherein the electronics include the intelligent multiplexer.

E10. The brain electrode device of embodiment E3, further comprising: marks provided on the tabs and configured to measure an effective insertion distance of the tabs.

Example Embodiments F Electrode Array with Ground Reference

FI. A brain electrode device comprising: a plurality of contact points; a plurality of sub-circuits including sensor ports configured to connect to the contact points, respectively; a ground electrode wire; and a signal electrode wire routed parallel with the ground electrode wire and spaced apart from the ground electrode wire at a predetermined distance.

F2. The brain electrode device of embodiment FI, wherein the predetermined distance ranges between 1 micron and 10 millimeters.

F3. The brain electrode device of any one of embodiments F1-F2, further comprising: an intelligent multiplexer configured to aggregate signals from the plurality of sub circuits and generate an aggregate signal, wherein the aggregate signal is transmitted to a signal acquisition device.

F4. The brain electrode device of any one of embodiments F1-F3, wherein the plurality of sub -circuits includes sample/hold circuits configured to sample an input signal and hold its value.

F5. The brain electrode device of embodiment F4, further comprising: a snapshot signal circuit configured to transmit a snapshot signal to instruct the sample/hold circuits with timings of sampling the input signals.

F6. The brain electrode device of embodiment F5, wherein the snapshot signal is configured to reset the sample/hold circuits during a next snapshot pulse. F7. The brain electrode device of any one of embodiments F1-F6, wherein the signal acquisition system includes an analog-to-digital converter and a digital signal processor.

[0115] FIG. 12 is a block diagram of computing devices 1200, 1250 that may be used to implement the systems and methods described in this document, as either a client or as a server or plurality of servers. Computing device 1200 is intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. Computing device 1250 is intended to represent various forms of mobile devices, such as personal digital assistants, cellular telephones, smartphones, and other similar computing devices. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit implementations described and/or claimed in this document.

[0116] Computing device 1200 includes a processor 1202, memory 1204, a storage device 1206, a high-speed interface 1208 connecting to memory 1204 and high-speed expansion ports 1210, and a low speed interface 1212 connecting to low speed bus 1214 and storage device 1206. Each of the components 1202, 1204, 1206, 1208, 1210, and 1212, are interconnected using various busses, and may be mounted on a common motherboard or in other manners as appropriate. The processor 1202 can process instructions for execution within the computing device 1200, including instructions stored in the memory 1204 or on the storage device 1206 to display graphical information for a GUI on an external input/output device, such as display 1216 coupled to high-speed interface 1208. In other implementations, multiple processors and/or multiple buses may be used, as appropriate, along with multiple memories and types of memory. Also, multiple computing devices 1200 may be connected, with each device providing portions of the necessary operations (e.g., as a server bank, a group of blade servers, or a multi-processor system).

[0117] The memory 1204 stores information within the computing device 1200. In one implementation, the memory 1204 is a volatile memory unit or units. In another implementation, the memory 1204 is a non-volatile memory unit or units. The memory 1204 may also be another form of computer-readable medium, such as a magnetic or optical disk. [0118] The storage device 1206 is capable of providing mass storage for the computing device 1200. In one implementation, the storage device 1206 may be or contain a computer- readable medium, such as a floppy disk device, a hard disk device, an optical disk device, or a tape device, a flash memory or other similar solid state memory device, or an array of devices, including devices in a storage area network or other configurations. A computer program product can be tangibly embodied in an information carrier. The computer program product may also contain instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer- or machine-readable medium, such as the memory 1204, the storage device 1206, or memory on processor 1202. [0119] The high-speed controller 1208 manages bandwidth- intensive operations for the computing device 1200, while the low speed controller 1212 manages lower bandwidth intensive operations. Such allocation of functions is an example only. In one implementation, the high-speed controller 1208 is coupled to memory 1204, display 1216 (e.g., through a graphics processor or accelerator), and to high-speed expansion ports 1210, which may accept various expansion cards (not shown). In the implementation, low-speed controller 1212 is coupled to storage device 1206 and low-speed expansion port 1214. The low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet) may be coupled to one or more input/output devices, such as a keyboard, a pointing device, a scanner, or a networking device such as a switch or router, e.g., through a network adapter.

[0120] The computing device 1200 may be implemented in a number of different forms, as shown in the figure. For example, it may be implemented as a standard server 1220, or multiple times in a group of such servers. It may also be implemented as part of a rack server system 1224. In addition, it may be implemented in a personal computer such as a laptop computer 1222. Alternatively, components from computing device 1200 may be combined with other components in a mobile device (not shown), such as device 1250. Each of such devices may contain one or more of computing device 1200, 1250, and an entire system may be made up of multiple computing devices 1200, 1250 communicating with each other.

[0121] Computing device 1250 includes a processor 1252, memory 1264, an input/output device such as a display 1254, a communication interface 1266, and a transceiver 1268, among other components. The device 1250 may also be provided with a storage device, such as a microdrive or other device, to provide additional storage. Each of the components 1250, 1252, 1264, 1254, 1266, and 1268, are interconnected using various buses, and several of the components may be mounted on a common motherboard or in other manners as appropriate. [0122] The processor 1252 can execute instructions within the computing device 1250, including instructions stored in the memory 1264. The processor may be implemented as a chipset of chips that include separate and multiple analog and digital processors.

Additionally, the processor may be implemented using any of a number of architectures. For example, the processor may be a CISC (Complex Instruction Set Computers) processor, a RISC (Reduced Instruction Set Computer) processor, or aMISC (Minimal Instruction Set Computer) processor. The processor may provide, for example, for coordination of the other components of the device 1250, such as control of user interfaces, applications run by device 1250, and wireless communication by device 1250.

[0123] Processor 1252 may communicate with a user through control interface 1258 and display interface 1256 coupled to a display 1254. The display 1254 may be, for example, a TFT (Thin-Film-Transistor Liquid Crystal Display) display or an OLED (Organic Light Emitting Diode) display, or other appropriate display technology. The display interface 1256 may comprise appropriate circuitry for driving the display 1254 to present graphical and other information to a user. The control interface 1258 may receive commands from a user and convert them for submission to the processor 1252. In addition, an external interface 1262 may be provide in communication with processor 1252, so as to enable near area communication of device 1250 with other devices. External interface 1262 may be provided, for example, for wired communication in some implementations, or for wireless communication in other implementations, and multiple interfaces may also be used.

[0124] The memory 1264 stores information within the computing device 1250. The memory 1264 can be implemented as one or more of a computer-readable medium or media, a volatile memory unit or units, or a non-volatile memory unit or units. Expansion memory 1274 may also be provided and connected to device 1250 through expansion interface 1272, which may include, for example, a SIMM (Single In Line Memory Module) card interface. Such expansion memory 1274 may provide extra storage space for device 1250, or may also store applications or other information for device 1250. Specifically, expansion memory 1274 may include instructions to carry out or supplement the processes described above, and may include secure information also. Thus, for example, expansion memory 1274 may be provide as a security module for device 1250, and may be programmed with instructions that permit secure use of device 1250. In addition, secure applications may be provided via the SIMM cards, along with additional information, such as placing identifying information on the SIMM card in a non-hackable manner.

[0125] The memory may include, for example, flash memory and/or NVRAM memory, as discussed below. In one implementation, a computer program product is tangibly embodied in an information carrier. The computer program product contains instructions that, when executed, perform one or more methods, such as those described above. The information carrier is a computer- or machine-readable medium, such as the memory 1264, expansion memory 1274, or memory on processor 1252 that may be received, for example, over transceiver 1268 or external interface 1262.

[0126] Device 1250 may communicate wirelessly through communication interface 1266, which may include digital signal processing circuitry where necessary. Communication interface 1266 may provide for communications under various modes or protocols, such as GSM voice calls, SMS, EMS, or MMS messaging, CDMA, TDMA, PDC, WCDMA, CDMA2000, or GPRS, among others. Such communication may occur, for example, through radio-frequency transceiver 1268. In addition, short-range communication may occur, such as using a Bluetooth, WiFi, or other such transceiver (not shown). In addition, GPS (Global Positioning System) receiver module 1270 may provide additional navigation- and location- related wireless data to device 1250, which may be used as appropriate by applications running on device 1250.

[0127] Device 1250 may also communicate audibly using audio codec 1260, which may receive spoken information from a user and convert it to usable digital information. Audio codec 1260 may likewise generate audible sound for a user, such as through a speaker, e.g., in a handset of device 1250. Such sound may include sound from voice telephone calls, may include recorded sound (e.g., voice messages, music files, etc.) and may also include sound generated by applications operating on device 1250.

[0128] The computing device 1250 may be implemented in a number of different forms, as shown in the figure. For example, it may be implemented as a cellular telephone 1280. It may also be implemented as part of a smartphone 1282, personal digital assistant, or other similar mobile device.

[0129] Additionally computing device 1200 or 1250 can include Universal Serial Bus (USB) flash drives. The USB flash drives may store operating systems and other applications. The USB flash drives can include input/output components, such as a wireless transmitter or USB connector that may be inserted into a USB port of another computing device.

[0130] Various implementations of the systems and techniques described here can be realized in digital electronic circuitry, integrated circuitry, specially designed ASICs (application specific integrated circuits), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include implementation in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0131] These computer programs (also known as programs, software, software applications or code) include machine instructions for a programmable processor, and can be implemented in a high-level procedural and/or object-oriented programming language, and/or in assembly/machine language. As used herein, the terms “machine-readable medium” “computer-readable medium” refers to any computer program product, apparatus and/or device (e.g., magnetic discs, optical disks, memory, Programmable Logic Devices (PLDs)) used to provide machine instructions and/or data to a programmable processor, including a machine-readable medium that receives machine instructions as a machine-readable signal. The term “machine-readable signal” refers to any signal used to provide machine instructions and/or data to a programmable processor.

[0132] To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0133] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a client computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (“LAN”), a wide area network (“WAN”), peer-to-peer networks (having ad-hoc or static members), grid computing infrastructures, and the Internet.

[0134] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

[0135] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular implementations of particular inventions. Certain features that are described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable sub-combination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a sub-combination or variation of a sub-combination.

[0136] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0137] Thus, particular implementations of the subject matter have been described. Other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

[0138] What is claimed is: