SECONDARY BATTERY MOUNTED CHIP MANUFACTURING METHOD

Title:

SECONDARY BATTERY MOUNTED CHIP MANUFACTURING METHOD

Document Type and Number:

WIPO Patent Application WO/2017/022347

Kind Code:

A1

Abstract:

Provided is a manufacturing method enabling simultaneous and uniform manufacturing of oxide semiconductor secondary batteries on multiple chips. This manufacturing method is for chips having, laminated on circuits thereof, oxide semiconductor secondary batteries each formed through lamination of a first electrode 52, charging function layers (54, 56, 58), and a second electrode 60, and comprises: a lamination process in which the respective oxide semiconductor secondary batteries are integrally laminated and formed on regions corresponding to multiple chips 22 formed on a wafer 20 without individually forming each of the oxide semiconductor secondary batteries on a region corresponding to one of the chips 22; and a dividing process in which pattern etching is performed on the integrally formed oxide semiconductor secondary batteries so as to keep the regions corresponding to the respective chips 22 but remove the regions not corresponding to the chips 22 to divide the individual oxide semiconductor secondary batteries (50-1, 50-2) corresponding to the respective chips 22.

Inventors:

TSUNOKUNI KAZUYUKI (JP)
INOUE TATSUO (JP)
SAITOH TOMOKAZU (JP)
OGASAWARA JURI (JP)
TONOKAWA TAKASHI (JP)
KUDOH TAKUO (JP)

Application Number:

PCT/JP2016/068219

Publication Date:

February 09, 2017

Filing Date:

June 20, 2016

Export Citation:

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Assignee:

NIHON MICRONICS KK (JP)

International Classes:

H01L21/822; H01L21/8234; H01L27/04; H01L27/06

Domestic Patent References:

WO2014099974A1	2014-06-26
WO2013183132A1	2013-12-12
WO2012046325A1	2012-04-12
WO2015129051A1	2015-09-03

Foreign References:

JP2006286690A	2006-10-19
JP2011501388A	2011-01-06
JP2000106366A	2000-04-11
JP2014158379A	2014-08-28
JP2002353328A	2002-12-06

Other References: