Related Applications

[0001] This application claims the benefit of provisional patent application serial number 63/157,057, filed March 5, 2021 , the disclosure of which is hereby incorporated herein by reference in its entirety.

Field of the Disclosure

[0002] The present disclosure relates to a fabricating procedure of a radio frequency (RF) device, and more particularly to a selective etching process for silicon germanium (SiGe) and doped epitaxial silicon in the fabricating procedure of the radio frequency (RF) device.

Background

[0003] The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high level performance in the RF technologies. Fabrications of the RF devices on conventional silicon substrates may benefit from low cost of silicon materials, a large-scale capacity of wafer production, well-established semiconductor design tools, and well- established semiconductor manufacturing techniques.

[0004] Despite the benefits of using conventional silicon substrates for RF device fabrications, it is well known in the industry that conventional silicon substrates may have two undesirable properties for RF devices: harmonic distortion and low resistivity values. The harmonic distortion is a critical impediment to achieve high level linearity in the RF devices built over silicon substrates. In addition, high speed and high-performance transistors are more densely integrated in RF devices. Consequently, the amount of heat generated by the RF devices will increase significantly due to the large number of transistors integrated in the RF devices, the large amount of power passing through the transistors, and/or the high operation speed of the transistors. Accordingly, it is desirable to package the RF devices in a configuration for better heat dissipation.

[0005] Radio frequency silicon on insulator (RFSOI) wafers are conventionally used for fabricating RF devices. Flowever, with the looming shortage of conventional RFSOI wafers expected in the coming years, alternative technologies are being devised to get around the need for high resistivity using silicon wafers, the trap rich layer formation, and Smart-Cut SOI wafer process. One alternative technology is based on the use of a silicon germanium (SiGe) layer instead of a buried oxide layer (BOX) between a silicon substrate and a silicon epitaxial layer; however, this technology will also suffer from the deleterious distortion effects due to the silicon substrate, similar to what is observed in an RFSOI technology.

[0006] In addition, due to the narrow gap nature of the SiGe material, it is possible that the SiGe between the silicon substrate and the silicon epitaxial layer may be conducting, which may cause appreciable current leakage. Therefore, in some applications, such as switch field-effect transistor (FET) applications, the presence of the SiGe layer can cause harm to the devices. [0007] To reduce deleterious harmonic distortion of the RF devices and to utilize the Si-SiGe-Si structure to manufacture RF devices without undesirable current leakage in the RF devices, it is therefore an object of the present disclosure to provide an improved fabricating method for enhancing thermal and electrical performance of the devices.

[0008] The present disclosure relates to a fabricating procedure of a radio frequency (RF) device, and more particularly to a selective etching process for silicon germanium (SiGe) and doped epitaxial silicon in the fabricating procedure of the radio frequency (RF) device. According to an exemplary fabricating process, a precursor wafer, which includes a number of device regions, a number of interfacial layers, and a silicon handle substrate, is firstly provided. Each device region includes an active layer that is fabricated from doped epitaxial silicon. Each interfacial layer formed of silicon germanium (SiGe) is directly over one active layer of a corresponding device region, and the silicon handle substrate is over each interfacial layer. Next, the silicon handle substrate is removed completely, and each interfacial layer is removed completely to expose the active layer. An etch passivation film is then formed directly over the active layer of each device region. Herein, both removing each interfacial layer and forming the etch passivation film utilize a same reactive chemistry combination. This reactive chemistry combination is chosen in a manner that the reactive chemistry combination reacts differently to the interfacial layer and the active layer. The reactive chemistry combination is capable of producing a variable net performance, which is an etching performance of the interfacial layer or a forming performance of the etch passivation film over the active layer.

[0009] In one embodiment of the exemplary fabricating process, the interfacial layer is removed by a dry etching process.

[0010] In one embodiment of the exemplary fabricating process, the reactive chemistry combination is a mixed gas flow of sulfur hexafluoride (SF6), nitrogen (N2), and boron chloride (BC ), such that reactive radicals fluorine (F), chlorine (Cl), boron nitride (BN), and boron chloride (BCIx) are provided in removing the interfacial layer and forming the etch passivation film. The F and Cl radicals are capable of etching doped epitaxial silicon and SiGe, and the BN and BCIx radicals are capable of forming a passivation material on doped epitaxial silicon and SiGe. A competition between an etching rate of the F and Cl radicals and a forming rate of the BN and BCIx radicals determines the net performance. For the interfacial layer, the etching rate of the F and Cl radicals is faster than the forming rate of the BN and BCIx, such that the net performance is the etching performance leading to the removal of the interfacial layer. For the active layer, the etching rate of the F and Cl radicals is slower than the forming rate of the BN and BCIx, such that the net performance is the forming performance of the etch passivation film over the active layer. [0011] In one embodiment of the exemplary fabricating process, in the mixed gas flow, SF6 has a flow rate between 5 seem and 60 seem, N2 has a flow rate between 20 seem and 90 seem, and BC has a flow rate between 20 seem and 90 seem.

[0012] In one embodiment of the exemplary fabricating process, the flow rate of SFe, the flow rate of N2, and the flow rate of BCb are constant in removing the interfacial layer and forming the etch passivation film.

[0013] In one embodiment of the exemplary fabricating process, an oxygen (O2) gas flow and an argon (Ar) gas flow are used with the reactive chemistry combination in removing the interfacial layer and forming the etch passivation film.

[0014] In one embodiment of the exemplary fabricating process, the O2 gas flow has a flow rate between 50 seem and 400 seem, and the Ar gas flow has a flow rate between 10 seem and 60 seem.

[0015] According to another embodiment, the exemplary fabricating process further includes a breakthrough etching step before the removal of the interfacial layer. The breakthrough etching step removes a surface oxide layer, which is formed after the removal of the silicon handle substrate and directly on the interfacial layer, to expose the interfacial layer.

[0016] In one embodiment of the exemplary fabricating process, the surface oxide layer is removed by a dry etching process, and is pre-calibrated.

[0017] In one embodiment of the exemplary fabricating process, the surface oxide layer is removed using a SF6 gas flow.

[0018] In one embodiment of the exemplary fabricating process, during the breakthrough etching step, the SF6 gas flow has a flow rate between 5 seem and 40 seem.

[0019] In one embodiment of the exemplary fabricating process, an O2 gas flow and an Ar gas flow are used with the SF6 gas flow in the breakthrough etching step, where the O2 gas flow has a flow rate between 50 seem and 400 seem, and the Ar gas flow has a flow rate between 10 seem and 60 seem. [0020] In one embodiment of the exemplary fabricating process, the surface oxide layer and the interfacial layer are removed by a same dry etching process but utilize different reactive chemistry combinations.

[0021] In another aspect, any of the foregoing aspects individually or together, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various features and elements as disclosed herein may be combined with one or more other disclosed features and elements unless indicated to the contrary herein.

[0022] Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures.

[0023] The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

[0024] Figure 1 shows an exemplary radio frequency (RF) device with enhanced thermal and electrical performance according to one embodiment of the present disclosure.

[0025] Figure 2 provides a flow diagram that illustrates an exemplary fabricating procedure of the RF device shown in Figure 1 according to one embodiment of the present disclosure.

[0026] Figures 3-14 illustrate the steps associated with the fabricating procedure provided in Figure 2.

[0027] It will be understood that for clear illustrations, Figures 1 -14 may not be drawn to scale.

[0028] The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

[0029] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. [0030] It will be understood that when an element such as a layer, region, or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being "over" or extending "over" another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly over" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0031] Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical" may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including" when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0034] Embodiments are described herein with reference to schematic illustrations of embodiments of the disclosure. As such, the actual dimensions of the layers and elements can be different, and variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are expected. For example, a region illustrated or described as square or rectangular can have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the disclosure. Additionally, sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and, thus, are provided to illustrate the general structures of the present subject matter and may or may not be drawn to scale. Common elements between figures may be shown herein with common element numbers and may not be subsequently re described.

[0035] Figure 1 shows an exemplary RF device 10 formed from a silicon handle substrate-silicon germanium interfacial layer-silicon epitaxial layer (Si- SiGe-Si) wafer (processing details are described in following paragraphs) according to one embodiment of the present disclosure. For the purpose of this illustration, the exemplary RF device 10 includes a mold device die 12 with a device region 14, device passivation layers 15, and a first mold compound 16, and a multilayer redistribution structure 18 formed under the mold device die 12. [0036] In detail, the device region 14 includes a front-end-of-line (FEOL) portion 20 and a back-end-of-line (BEOL) portion 22 underneath the FEOL portion 20. In one embodiment, the FEOL portion 20 is configured to provide a switch field-effect transistor (FET), and includes an active layer 24 and a contact layer 26. Herein, the active layer 24 has a source 28 (e.g., N+ doped silicon), a drain 30 (e.g., N+ doped silicon), and a channel 32 (e.g., P doped silicon) between the source 28 and the drain 30. The source 28, the drain 30, and the channel 32 are formed from a same silicon epitaxial layer. The contact layer 26 is formed underneath the active layer 24 and includes a gate structure 34, a source contact 36, a drain contact 38, and a gate contact 40. The gate structure 34 may be formed of silicon oxide, and extends horizontally underneath the channel 32 (from underneath the source 28 to underneath the drain 30). The source contact 36 is connected to and under the source 28, the drain contact 38 is connected to and under the drain 30, and the gate contact 40 is connected to and under the gate structure 34. An insulating material 42 may be formed around the source contact 36, the drain contact 38, the gate structure 34, and the gate contact 40 to electrically separate the source 28, the drain 30, and the gate structure 34. In different applications, the FEOL portion 20 may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor. [0037] In addition, the FEOL portion 20 also includes isolation sections 44, which reside over the insulating material 42 of the contact layer 26 and surround the active layer 24. The isolation sections 44, which may be formed of silicon dioxide, are configured to electrically separate the RF device 10, especially the active layer 24, from other devices formed in a common wafer (not shown). Flerein, the isolation sections 44 may extend from a top surface of the contact layer 26 and vertically beyond a top surface of the active layer 24 to define an opening 46 that is within the isolation sections 44 and over the active layer 24. [0038] Notice that the active layer 24 is formed from a silicon epitaxial layer of the Si-SiGe-Si wafer, while the silicon handle substrate and SiGe interfacial layer of the Si-SiGe-Si wafer are completely removed during the fabricating process of the RF device 10 (process details are described in following paragraphs).

[0039] In one embodiment, the device passivation layers 15 include a first device passivation layer 15-1 and a second device passivation layer 15-2. The first device passivation layer 15-1 extends over an entire backside of the device region 14, such that the first device passivation layer 15-1 continuously covers exposed surfaces within the opening 46 and top surfaces of the isolation sections 44. The first device passivation layer 15-1 may be formed of silicon dioxide and is configured to terminate the surface bonds at the top surface of the active layer 24, which may be responsible for unwanted leakage. The second device passivation layer 15-2 is formed directly over the first device passivation layer 15- 1. Flerein, the second device passivation layer 15-2 may be formed of silicon nitride and is configured to provide an excellent barrier to moisture and impurities, which could diffuse into the channel 32 of the active layer 24 and cause reliability concerns in the device.

[0040] The RF device 10 further includes an etch passivation film 48, which may be formed of boron nitride (BN) and boron chloride (BCIx, x 0-3), directly over the top surface of the active layer 24 and within the opening 46. As such, the first device passivation layer 15-1 is directly over the etch passivation film 48. The etch passivation film 48 is formed as a result of a selective etching process and protects the active layer 24 from being further etched (process details are described in following paragraphs).

[0041] The first mold compound 16 is formed over the device passivation layers 15, such that the first mold compound 16 fills the opening 46 and is in contact with the second device passivation layer 15-2. The first mold compound 16 may have a thermal conductivity greater than 1 W/m-K, or greater than 10 W/m-K. In addition, the first mold compound 16 may have a low dielectric constant less than 8, or between 3 and 5 to yield low RF coupling. In one embodiment, the first mold compound 16 may be formed of thermoplastics or thermoset polymer materials, such as PPS (poly phenyl sulfide), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, or diamond-like thermal additives, or the like. A thickness of the first mold compound 16 is based on the required thermal performance of the RF device 10, the device layout, the distance from the multilayer redistribution structure 18, as well as the specifics of the package and assembly. The first mold compound 16 may have a thickness between 200 pm and 500 pm. Notice that, silicon crystal, which has no nitrogen or oxygen content, does not exist between the first mold compound 16 and the top surface of the active layer 24. Each of the device passivation layers 15 is formed of silicon composite.

[0042] The BEOL portion 22 is underneath the FEOL portion 20 and includes multiple connecting layers 50 formed within dielectric layers 52. Some of the connecting layers 50 are encapsulated by the dielectric layers 52 (not shown), while some of the connecting layers 50 have a bottom portion not covered by the dielectric layers 52. Certain connecting layers 50 are electrically connected to the FEOL portion 20. For the purpose of this illustration, one of the connecting layers 50 is connected to the source contact 36, and another connecting layer 50 is connected to the drain contact 38.

[0043] The multilayer redistribution structure 18, which is formed underneath the BEOL portion 22 of the mold device die 12, includes a number of redistribution interconnections 54, a dielectric pattern 56, and a number of bump structures 58. Herein, each redistribution interconnection 54 is connected to a corresponding connecting layer 50 within the BEOL portion 22 and extends over a bottom surface of the BEOL portion 22. The connections between the redistribution interconnections 54 and the connecting layers 50 are solder-free. The dielectric pattern 56 is formed around and underneath each redistribution interconnection 54. A bottom portion of each redistribution interconnection 54 is exposed through the dielectric pattern 56. Each bump structure 58 is formed at a bottom of the multilayer redistribution structure 18 and electrically coupled to a corresponding redistribution interconnection 54 through the dielectric pattern 56. Consequently, the redistribution interconnections 54 are configured to connect the bump structures 58 to certain ones of the connecting layer 50 in the BEOL portion 22, which are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 via corresponding redistribution interconnections 54 and corresponding connecting layers 50. In addition, the bump structures 58 are separate from each other and extend underneath the dielectric pattern 56.

[0044] The multilayer redistribution structure 18 may be free of glass fiber or glass-free. Herein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections 54 may be formed of copper or other suitable metals. The dielectric pattern 56 may be formed of benzocyclobutene (BCB), polyimide, or other dielectric materials. The bump structures 58 may be solder balls or copper pillars. The multilayer redistribution structure 18 has a thickness between 2 pm and 300 pm.

[0045] Figure 2 provides a flow diagram that illustrates an exemplary fabricating procedure 200 of the RF device 10 shown in Figure 1 according to one embodiment of the present disclosure. Figures 3-14 illustrate the steps associated with the fabricating procedure 200 provided in Figure 2. Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in Figures 3-14. [0046] Initially, a Si-SiGe-Si wafer 62 is provided as illustrated in Figure 3 (Step 202). The Si-SiGe-Si wafer 62 includes a common silicon epitaxial layer 64, a common SiGe interfacial layer 66 over the common silicon epitaxial layer 64, and a silicon handle substrate 68 over the common SiGe interfacial layer 66. Herein, the common silicon epitaxial layer 64 is formed from a device grade silicon material, which has desired silicon epitaxial characteristics to form electronic devices. The common SiGe interfacial layer 66, which separates the common silicon epitaxial layer 64 from the silicon handle substrate 68, is formed from an alloy with any molar ratio of Si and Ge. The higher the Ge concentration, the better the etching selectivity between the silicon handle substrate 68 and the common SiGe interfacial layer 66 and between the common SiGe interfacial layer 66 and the common silicon epitaxial layer 64. However, the higher the Ge concentration, the more difficult the epitaxial growth of the common silicon epitaxial layer 64 becomes. In one embodiment, the common SiGe interfacial layer 66 may have a Ge concentration between 25% and 30%. The Ge concentration may be uniform throughout the common SiGe interfacial layer 66 or may be vertically graded so as to yield the necessary strain relief for the growth of the common silicon epitaxial layer 64. The silicon handle substrate 68 may consist of conventional low cost, low resistivity, and high dielectric constant silicon. The common silicon epitaxial layer 64 has higher resistivity, lower harmonic generation, and lower dielectric constant than the silicon handle substrate 68. A thickness of the common silicon epitaxial layer 64 may be between 700 nm and 2000 nm, a thickness of the common SiGe interfacial layer 66 may be between 100 nm and 1000 nm, and a thickness of the silicon handle substrate 68 may be between 200 pm and 500 pm.

[0047] Next, a complementary metal-oxide-semiconductor (CMOS) process is performed on the Si-SiGe-Si wafer 62 to provide a precursor wafer 70 with a number of device regions 14, as illustrated in Figure 4 (Step 204). For the purpose of this illustration, the FEOL portion 20 of each device region 14 is configured to provide a switch FET. In different applications, the FEOL portion 20 may have different FET configurations or provide different device components, such as a diode, a capacitor, a resistor, and/or an inductor.

[0048] In this embodiment, the isolation sections 44 of each device region 14 extend through the common silicon epitaxial layer 64 and the common SiGe interfacial layer 66 and extend into the silicon handle substrate 68. As such, the common SiGe interfacial layer 66 separates into a number of individual SiGe interfacial layers 66I, and the common silicon epitaxial layer 64 separates into a number of individual silicon epitaxial layers 64I, each of which is used to form a corresponding active layer 24 (i.e., a doped source-drain epitaxial silicon layer) in one device region 14. The isolation sections 44 may be formed by shallow trench isolation (STI).

[0049] The top surface of the active layer 24 is in contact with a corresponding SiGe interfacial layer 66I. The silicon handle substrate 68 resides over each SiGe interfacial layer 66I, and portions of the silicon handle substrate 68 may reside over the isolation sections 44. The BEOL portion 22 of the device region 14, which includes at least the multiple connecting layers 50 and the dielectric layers 52, is formed under the contact layer 26 of the FEOL portion 20. Bottom portions of certain connecting layers 50 are exposed through the dielectric layers 52 at the bottom surface of the BEOL portion 22.

[0050] After the precursor wafer 70 is completed, the precursor wafer 70 is then bonded to a temporary carrier 72, as illustrated in Figure 5 (Step 206). The precursor wafer 70 may be bonded to the temporary carrier 72 via a bonding layer 74, which provides a planarized surface to the temporary carrier 72. The temporary carrier 72 may be a thick silicon wafer from a cost and thermal expansion point of view, but may also be construed of glass, sapphire, or other suitable carrier material. The bonding layer 74 may be a span-on polymeric adhesive film, such as the Brewer Science WaferBOND line of temporary adhesive materials.

[0051] The silicon handle substrate 68 is then selectively removed to provide an etched wafer 76, wherein the selective removal is stopped on each SiGe interfacial layer 66I, as illustrated in Figure 6 (Step 208). Removing the silicon handle substrate 68 may be provided by chemical mechanical grinding and an etching process with a wet/dry etchant chemistry, which may be potassium hydroxide (KOH), sodium hydroxide (NaOH), acetylcholine (ACH), tetramethylammonium hydroxide (TMAH), or xenon difluoride (XeF2), or provided by the etching process itself. As an example, the silicon handle substrate 68 may be ground to a thinner thickness to reduce the following etching time. An etching process is then performed to completely remove the remaining silicon handle substrate 68.

[0052] Since the silicon handle substrate 68 and the SiGe interfacial layers 66I have different ingredients/characteristics, they will have different reactions to a same etching technique. For instance, the SiGe interfacial layers 66I have a much slower etching speed than the silicon handle substrate 68 with a same etchant (e.g., TMAFI, KOFI, NaOFI, ACFI, or XeF2). Consequently, the etching system is capable of identifying the presence of the SiGe interfacial layers 66I and capable of indicating when to stop the etching process. Flerein each SiGe interfacial layer 66I functions as an etch stop layer for the corresponding active layer 24 (i.e., the doped source-drain epitaxial silicon layer).

[0053] In addition, the isolation sections 44 may be formed of silicon dioxide, which may resist etching chemistries such as TMAFI, KOFI, NaOFI, ACFI, or XeF2. During the removal process, the isolation sections 44 are hardly removed and protect sides of each active layer 24. If the isolation sections 44 extend vertically beyond the SiGe interfacial layers 66I, the removal of the silicon handle substrate 68 will provide the opening 46 over each active layer 24 and within the isolation sections 44. The bonding layer 74 and the temporary carrier 72 protect the bottom surface of each BEOL portion 22.

[0054] Due to the narrow gap nature of the SiGe material, it is possible that the SiGe interfacial layers 66I may be conducting. Each SiGe interfacial layer 66I may cause appreciable leakage between the source 28 and the drain 30 of the active layer 24. Therefore, in some applications, especially FET applications, it is desired to completely remove the SiGe interfacial layers 66I. [0055] After the removal of the silicon handle substrate 68, there might be a surface oxide layer (i.e., silicon oxide layer) 67 formed on each SiGe interfacial layer 66I because the SiGe interfacial layer 66I is exposed to the atmosphere. Accordingly, before removing the SiGe interfacial layers 66I, there is a breakthrough etching step to remove each surface oxide layer 67 on the SiGe interfacial layers 66I, as illustrated in Figure 7 (Step 210).

[0056] The surface oxide layer 67 may be removed by a dry etching process utilizing a plasma etch system with a sulfur hexafluoride (SF6) gas flow. Flerein, the SFe gas flow may be provided with an argon (Ar) gas flow and an oxygen (O2) gas flow, where the Ar gas flow acts as a carrier gas flow, and the O2 gas flow is used to dilute the SF6 gas flow and implement uniformity during the processing. In this breakthrough etching step, the SF6 gas flow has a flow rate of 5-60 standard cubic centimeter per minute (seem), the 02gas flow has a flow rate of 50-400 seem, and the Ar gas flow has a flow rate of 10-60 seem. Since the surface oxide layer 67 is typically very thin (e.g., about a few A), a duration of the breakthrough etching step is very short and can be pre-calibrated in the plasma etch system (e.g., by using a timer). The isolation sections 44 formed of silicon dioxide may only be minimally etched in this breakthrough etching step (Step 210) and still protect sides of each active layer 24.

[0057] As described above, each active layer 24 is directly underneath the SiGe interfacial layer 66I that may cause unwanted current leakage in the active layer 24. It is therefore highly desired to completely remove each SiGe interfacial layer 66I without harming the active layer 24. The SiGe interfacial layers 66I may be removed by the same dry etching process used to remove the surface oxide layer 67 in the same plasma etch system, but by utilizing a different reactive chemistry combination. The reactive chemistry combination provides the removal of the SiGe interfacial layers 66I followed by the etch passivation film 48 formed on the surface of the minimally etched active layer 24.

[0058] Table 1 shows detailed conditions of the dry etching process in the breakthrough etching step (Step 210), a SiGe etching step (Step 212), and a passivation film forming step (Step 214). In the SiGe etching step and the passivation film forming step, the reactive chemistry combination is a mixed gas flow of SFe, Nitrogen (N2), and boron chloride (BC ). These reactive gas components may be carried by the Ar gas flow and may be diluted to various concentration degrees by using the C>2gas flow. Note that the reactions of the Ar and O2 gas flows are negligible during Steps 210-214. The following reactions are expected to occur in the plasma etch system once power is applied:

SFe => F ^* +SFx BCk=> BCly +Cl ^*

BCI _y +N ₂ => BN +BCI _y +Ct Various reactive radicals fluorine (F), chlorine (Cl), BN, and boron chloride (BCly) are generated, wherein ^* represents an excited state of the radicals (with high energy), x represents a number between 0 and 6, and y represents a number between 0 and 3. Flerein, the F and Cl radicals can etch silicon and SiGe, while the BN and BCIx radicals can form an etch passivation film. A competition between the etching rate of the F and Cl radicals and the forming rate of the BN and BCIx radicals determines a net performance, which can lead to an SiGe etching result or a passivation film forming result.

Table 1

[0059] The reactive chemistry combination is carefully chosen in a manner that it reacts differently to the SiGe interfacial layer 66I and the active layer 24 (i.e., the doped source-drain epitaxial silicon layer) causing a variable net performance. In other words, the reactive chemistry combination is optimized to achieve an infinite selectivity between SiGe and silicon by shifting the net performance to an etching performance of the SiGe interfacial layer 66I, and to a forming performance of the etch passivation film 48 over the active layer 24. When the SiGe interfacial layers 66I are exposed to the reactive chemistry combination, the etching rate of the F and Cl radicals is faster than the forming rate of the BN and BCIx, such that the net performance is the etching performance leading to the removal of the SiGe interfacial layers 66I, as illustrated in Figure 8 (Step 212). A net etching speed of the SiGe interfacial layers 66I may be between 10 A/min and 300 A/min.

[0060] Once the SiGe interfacial layers 66I are completely removed, the active layers 24 are exposed to the reactive chemistry combination. For the active layers 24, the etching rate of the F and Cl radicals is slower than the forming rate of the BN and BCIx, such that the net performance is the forming performance of the etch passivation film 48 over each active layer 24, as illustrated in Figure 9 (Step 214). Therefore, each active layer 24 is not etched at all or only minimally etched at a top surface. Accordingly, superior etching selectivity is achieved between the SiGe interfacial layers 66I and the active layers 24. In a more general way, the superior etching selectivity can be achieved between SiGe material and doped silicon material by utilizing a special reactive chemistry combination (e.g., a gas combination of SF6, N2, and BC ). A net forming speed of the etch passivation film 48 may be between 1 A/min and 20 A/min. In one embodiment, the net forming speed of the etch passivation film 48 may be much slower than the net etching speed of the SiGe interfacial layer 66I.

[0061] During the SiGe etching step (Step 212) and the passivation film forming step (Step 214), the isolation sections 44 are not etched by the mixed gas flow. In the mixed gas flow, SF6 may have a flow rate of 5-60 seem, N2 may have a flow rate of 20-90 seem, BCb may have a flow rate of 20-90 seem, O2 may have a flow rate of 50-400 seem, and Ar may have a flow rate of 10-60 seem. By adjusting the flow ratio of respective gas flows, different etching/forming rates and selectivity can be achieved between the SiGe interfacial layers 66I and the active layers 24. In one embodiment, the reactive chemistry combination and the flow ratios of these reactive gas components may remain constant during the SiGe etching step (Step 212) and the passivation film forming step (Step 214). [0062] Next, the device passivation layers 15 are formed over the etch passivation film 48, as illustrated in Figures 10A and 10B (Step 216). The device passivation layers 15 continuously cover exposed surfaces within each opening 46 and the top surface of each isolation section 44. As shown in Figure 10A, the first device passivation layer 15-1 is firstly applied continuously over the exposed surfaces within each opening 46 and the top surface of each isolation section 44. The first device passivation layer 15-1 is in contact with the passivation layer 48 and always covers each active layer 24. The first device passivation layer 15-1 may be formed of silicon dioxide by a plasma enhanced deposition process, an anodic oxidation process, an ozone-based oxidation process, or a number of other proper techniques. The first device passivation layer 15-1 is configured to terminate the surface bonds at the top surface of the active layer 24, which may be responsible for unwanted leakage.

[0063] As shown in Figure 10B, the second device passivation layer 15-2 is then applied directly over the first device passivation layer 15-1. The second device passivation layer 15-2 also covers each active layer 24, side surfaces of each isolation section 44 within each opening 46, and the top surface of each isolation section 44. Flerein, the second device passivation layer 15-2 may be formed of silicon nitride and is configured to provide an excellent barrier to moisture and impurities, which could diffuse into the channel 32 of the active layer 24 and cause reliability concerns in the device. The second device passivation layer 15-2 may be formed by a chemical vapor deposition system such as a plasma enhanced chemical vapor deposition (PECVD) system, or an atomic layer deposition (ALD) system.

[0064] After the device passivation layers are formed, the first mold compound 16 is applied over the device passivation layers 15 to provide a mold device wafer 78, as illustrated in Figure 11 (Step 218). The mold device wafer 78 includes a number of the mold device dies 12, each of which includes the device region 14, a portion of the device passivation layers 15, and a portion of the first mold compound 16. Herein, the first mold compound 16 fills each opening 46, fully covers the device passivation layers 15, and is in contact with the second device passivation layer 15-2.

[0065] The first mold compound 16 may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. The first mold compound 16 may have a superior thermal conductivity greater than 1 W/m-K or greater than 10 W/m-K, and may have a dielectric constant less than 8 or between 3 and 5. During the molding process of the first mold compound 16, the temporary carrier 72 provides mechanical strength and rigidity to the etched wafer 76. A curing process (not shown) is followed to harden the first mold compound 16.

The curing temperature is between 100 ^Q C and 320 ^Q C depending on which material is used as the first mold compound 16. After the curing process, the first mold compound 16 may be thinned and/or planarized (not shown).

[0066] The temporary carrier 72 is then debonded from the mold device wafer 78, and the bonding layer 74 is cleaned from the mold device wafer 78, as illustrated in Figure 12 (Step 220). A number of debonding processes and cleaning processes may be applied depending on the nature of the temporary carrier 72 and the bonding layer 74 chosen in the earlier steps. For instance, the temporary carrier 72 may be mechanically debonded using a lateral blade process with the stack heated to a proper temperature. Other suitable processes involve radiation of UV light through the temporary carrier 72 if it is formed of a transparent material, or chemical debonding using a proper solvent. The bonding layer 74 may be eliminated by wet or dry etching processes, such as proprietary solvents and plasma washing. After the debonding and cleaning process, the bottom portions of certain ones of the connecting layers 50, which may be functioned as input/output (I/O) ports of the mold device die 12, are exposed through the dielectric layers 52 at the bottom surface of each BEOL portion 22. As such, each mold device die 12 in the mold device wafer 78 may be electrically verified to be working properly at this point.

[0067] With reference to Figures 13A-13C, the multilayer redistribution structure 18 is formed underneath the mold device wafer 78 according to one embodiment of the present disclosure (Step 222). Although the redistribution steps are illustrated in a series, the redistribution steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, redistribution steps within the scope of this disclosure may include fewer or more steps than those illustrated in Figures 13A-13C.

[0068] A number of the redistribution interconnections 54 are firstly formed underneath each BEOL portion 22, as illustrated in Figure 13A. Each redistribution interconnection 54 is electrically coupled to the exposed bottom portion of the corresponding connecting layer 50 within the BEOL portion 22 and may extend over the bottom surface of the BEOL portion 22. The connections between the redistribution interconnections 54 and the connecting layers 50 are solder-free. The dielectric pattern 56 is then formed underneath each BEOL portion 22 to partially encapsulate each redistribution interconnection 54, as illustrated in Figure 13B. As such, the bottom portion of each redistribution interconnection 54 is exposed through the dielectric pattern 56. In different applications, there may be extra redistribution interconnections (not shown) electrically coupled to the redistribution interconnection 54 through the dielectric pattern 56, and extra dielectric patterns (not shown) formed underneath the dielectric pattern 56, such that a bottom portion of each extra redistribution interconnection is exposed.

[0069] Next, a number of the bump structures 58 are formed to complete the multilayer redistribution structure 18 and provide a wafer-level fan-out (WLFO) package 80, as illustrated in Figure 13C. Each bump structure 58 is formed at the bottom of the multilayer redistribution structure 18 and electrically coupled to an exposed bottom portion of the corresponding redistribution interconnection 54 through the dielectric pattern 56. Consequently, the redistribution interconnections 54 are configured to connect the bump structures 58 to certain ones of the connecting layer 50 in the BEOL portion 22, which are electrically connected to the FEOL portion 20. As such, the bump structures 58 are electrically connected to the FEOL portion 20 via corresponding redistribution interconnections 54 and corresponding connecting layers 50. In addition, the bump structures 58 are separate from each other and extend underneath the dielectric pattern 56.

[0070] The multilayer redistribution structure 18 may be free of glass fiber or glass-free. Flerein, the glass fiber refers to individual glass strands twisted to become a larger grouping. These glass strands may then be woven into a fabric. The redistribution interconnections 54 may be formed of copper or other suitable metals, the dielectric pattern 56 may be formed of BCB, polyimide, or other dielectric materials, and the bump structures 58 may be solder balls or copper pillars. The multilayer redistribution structure 18 has a thickness between 2 pm and 300 pm. Figure 14 shows a final step to singulate the WLFO package 80 into individual RF devices 10 (Step 224). The singulating step may be provided by a probing and dicing process at certain isolation sections 44.

[0071] It is contemplated that any of the foregoing aspects, and/or various separate aspects and features as described herein, may be combined for additional advantage. Any of the various embodiments as disclosed herein may be combined with one or more other disclosed embodiments unless indicated to the contrary herein.

[0072] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.