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Patent Searching and Data


Title:
SELF-BALANCING DIFFERENTIAL SIGNAL INTEGRAL AMPLIFICATION CIRCUIT-BASED CHIP STATE MONITORING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2024/066241
Kind Code:
A1
Abstract:
The present application relates to the technical field of chips, and discloses a self-balancing differential signal integral amplification circuit-based chip state monitoring circuit. The chip state monitoring circuit is built into a chip. A state signal of the chip may be sensed and transmitted to a chip configuration circuit after undergoing amplification and analog-to-digital conversion, so that the chip configuration circuit performs state monitoring and promptly gives feedback or responds, thereby improving the reliability and increasing the service life of the chip. In the chip state monitoring circuit, a brand-new self-balancing differential signal integral amplification circuit is used. A built-in positive coefficient integral network and negative coefficient balancing network allow the self-balancing differential signal integral amplification circuit to enter a self-balancing stable state after being amplified to a required multiple, thereby amplifying a fixed multiple without timing reading, and a control manner is simple and flexible.

Inventors:
CAO ZHENGZHOU (CN)
XIA FEIGE (CN)
SHAN YUEER (CN)
YAN HUA (CN)
Application Number:
PCT/CN2023/082992
Publication Date:
April 04, 2024
Filing Date:
March 22, 2023
Export Citation:
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Assignee:
WUXI ESIONTECH CO LTD (CN)
International Classes:
H03G3/30
Foreign References:
CN115567018A2023-01-03
US8841962B12014-09-23
US20200162093A12020-05-21
CN103199806A2013-07-10
CN104485135A2015-04-01
US20110279148A12011-11-17
Attorney, Agent or Firm:
WUXI HUAYUAN PATENT AND TRADEMARK AGENCY (GENERAL PARTNERSHIP) (CN)
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