Title:
SEMICONDUCTOR APPARATUS
Document Type and Number:
WIPO Patent Application WO/2022/113519
Kind Code:
A1
Abstract:
The present invention increases the reliability of a semiconductor apparatus in which a semiconductor chip is stacked on a wiring layer. This semiconductor apparatus comprises: a wiring layer; a semiconductor chip stacked in a predetermined region on a wiring surface of the wiring layer; and a signal line wired on the wiring surface and forming an angle where the signal line straddles a boundary line of the predetermined region in at least one of two regions divided by the boundary line, the angle being less than a predetermined angle. The semiconductor chip is stacked in a predetermined region on the wiring surface of the wiring layer. The signal line forms an angle where the signal line straddles a boundary line of the predetermined region in at least one of two regions divided by the boundary line, the angle being less than a predetermined angle.
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Inventors:
ONO KOICHI (JP)
KOTANAGI MIKA (JP)
KOTANAGI MIKA (JP)
Application Number:
PCT/JP2021/036399
Publication Date:
June 02, 2022
Filing Date:
October 01, 2021
Export Citation:
Assignee:
SONY GROUP CORP (JP)
International Classes:
H01L23/12; H01L25/065; H01L25/07; H01L25/18
Domestic Patent References:
| WO2013057867A1 | 2013-04-25 |
Foreign References:
| US10475768B2 | 2019-11-12 | |||
| US10304801B2 | 2019-05-28 | |||
| JP2002170826A | 2002-06-14 | |||
| JP2019075444A | 2019-05-16 | |||
| JP2005277429A | 2005-10-06 | |||
| JP2018026484A | 2018-02-15 | |||
| US9922964B1 | 2018-03-20 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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