Title:
SEMICONDUCTOR DEVICE, BATTERY PROTECTOIN CIRCUIT, AND POWER MANAGEMENT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2022/210367
Kind Code:
A1
Abstract:
A chip size package-type semiconductor device (1) that can be mounted face-down comprises a semiconductor layer (40) and N (N is an integer of three or more) vertical MOS transistors formed in the semiconductor layer (40). Each of the N vertical MOS transistors comprises, on an upper surface of the semiconductor layer (40), a gate pad electrically connected to a gate electrode of the vertical MOS transistor, and one or more source pads electrically connected to a source electrode of the vertical MOS transistor. The semiconductor layer (40) includes a semiconductor substrate (32), the semiconductor substrate (32) functioning as a common drain region for the N vertical MOS transistors. In a plan view of the semiconductor layer (40), the area of each of the N vertical MOS transistors is in accordance with a maximum specification current of each of the N vertical MOS transistors, and increases as the maximum specification current increases.
Inventors:
YAMAMOTO KOUKI
TAKATA HARUHISA
TAKATA HARUHISA
Application Number:
PCT/JP2022/014447
Publication Date:
October 06, 2022
Filing Date:
March 25, 2022
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L29/78; H01L21/8234; H01L27/088; H01L29/739
Domestic Patent References:
| WO2020129786A1 | 2020-06-25 |
Foreign References:
| JP2013247309A | 2013-12-09 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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