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Patent Searching and Data


Title:
SEMICONDUCTOR DEVICE, IMAGING DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/014118
Kind Code:
A1
Abstract:
The present invention reduces the parasitic capacitance in a silicon through electrode (TSV). This semiconductor device is provided with a predetermined layer. A via vertically penetrates the predetermined layer. A conductor is in contact with an upper surface-side material and a lower surface-side material of the vertically penetrated layer. The conductor forms a hollow part between itself and the inner surface of the via without coming into contact with the inner surface of the via, said hollow part vertically penetrating the layer. At least one of the upper surface-side material and the lower surface-side material of the layer is a conductive material; and at least a part of the conductive material is provided with an opening to the hollow part. This opening is used for the purpose of supplying an etchant during etching.

Inventors:
GOCHO TETSUO (JP)
Application Number:
PCT/JP2021/016718
Publication Date:
January 20, 2022
Filing Date:
April 27, 2021
Export Citation:
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Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L21/3205; H01L21/768; H01L23/522; H01L23/532; H01L27/146
Foreign References:
JP2019075515A2019-05-16
JP2016032087A2016-03-07
JP2014512692A2014-05-22
JP2013115382A2013-06-10
US20120292782A12012-11-22
JP2015511765W
Other References:
See also references of EP 4184554A4
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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