Title:
SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2004/084314
Kind Code:
A1
Abstract:
A semiconductor device comprising a nonvolatile memory element and a peripheral circuit including a field-effect transistor having an insulated gate, and a method for manufacturing the semiconductor device. A semiconductor device comprising a memory element having a high holding capability and a field-effect transistor having an insulated gate with a high drive current. A semiconductor device has a semiconductor substrate (1) having first and second regions (AR1, AR2), a floating gate structure (4, 5, 6, 7, 8) for a nonvolatile memory element formed on the first region, a control gate structure (14) coupled to the floating gate structure, and insulated gate electrodes (12, 14) for a logical circuit formed on the second region. The floating gate structure has a bird's beak larger than the insulated gate electrode.
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Inventors:
HASHIMOTO HIROSHI (JP)
TAKADA KAZUHIKO (JP)
TAKADA KAZUHIKO (JP)
Application Number:
PCT/JP2003/003382
Publication Date:
September 30, 2004
Filing Date:
March 19, 2003
Export Citation:
Assignee:
FUJITSU LTD (JP)
HASHIMOTO HIROSHI (JP)
TAKADA KAZUHIKO (JP)
HASHIMOTO HIROSHI (JP)
TAKADA KAZUHIKO (JP)
International Classes:
H01L21/28; H01L21/8247; H01L27/115; H01L29/51; H01L29/788; H01L29/792; (IPC1-7): H01L29/788; H01L29/792; H01L27/115; H01L21/8247
Foreign References:
| JP2003017596A | 2003-01-17 | |||
| JPH03214777A | 1991-09-19 | |||
| JP2000340773A | 2000-12-08 | |||
| JPH1154637A | 1999-02-26 | |||
| US5976934A | 1999-11-02 |
Attorney, Agent or Firm:
Takahashi, Keishiro (4th Fl. Okachimachi Tohsei Bldg., 3-12-1, Tait, Taito-ku Tokyo, JP)
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