Title:
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND PLASMA PROCESSING DEVICE
Document Type and Number:
WIPO Patent Application WO/2021/048995
Kind Code:
A1
Abstract:
In the present invention, in a manufacturing process of a three-dimensional structure device, such as a GAA type FET or a nanofork type FET having a layered channel in which a thin line or sheet-like channel is layered on the substrate in the vertical direction, separately-configured work function control metals are made without widening the gap between FETs having different threshold voltages. To this end, the manufacturing method includes: a first step S10 for performing anisotropic etching to form an opening in a mask material 23 until a work function control metal film 22 is exposed; a second step S11 for depositing a protective film 26; a third step S12 for performing anisotropic etching to remove the protective film while leaving the protective film deposited on the side wall of the mask material having the opening formed in the first step; and a fourth step S13 for performing isotropic etching to selectively remove the mask material between channels for the protective film and the work function control metal film.
Inventors:
MIURA MAKOTO (JP)
SATO KIYOHIKO (JP)
SONODA YASUSHI (JP)
SAKAI SATOSHI (JP)
SATO KIYOHIKO (JP)
SONODA YASUSHI (JP)
SAKAI SATOSHI (JP)
Application Number:
PCT/JP2019/035998
Publication Date:
March 18, 2021
Filing Date:
September 13, 2019
Export Citation:
Assignee:
HITACHI HIGH TECH CORP (JP)
International Classes:
H01L21/336; H01L21/8234; H01L27/088; H01L29/78
Domestic Patent References:
| WO2019116827A1 | 2019-06-20 |
Foreign References:
| US20170250290A1 | 2017-08-31 | |||
| JP2006080519A | 2006-03-23 | |||
| JP2011066151A | 2011-03-31 | |||
| JP2019515494A | 2019-06-06 |
Attorney, Agent or Firm:
POLAIRE I.P.C. (JP)
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