SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SEMICONDUCTOR DEVICE

Field of the Disclosure This disclosure relates to semiconductor device and methods of forming a semiconductor device.

Background

Semiconductor devices such as Metal Oxide Semiconductor Field Effect

Transistors (MOSFETs) are commonly used as power devices in applications, such as automotive electronics, power supplies, telecommunications, which applications require devices to operate at currents in the range of tenths up to hundreds of amperes (A).

Conventionally, by applying a voltage to the gate electrode of a MOSFET device, the device is turned on and a channel will be formed connecting the source and the drain regions allowing a current to flow. A lightly doped drift region is formed between the drain region and the channel. The drift region is required to be lightly doped in order to lower the maximum electric field that develops across the PN junction (p-body/n-epi) and thus, to ensure a high breakdown voltage. Once the MOSFET device is turned on, the relation between the current and the voltage is nearly linear which means that the device behaves like a resistance. The resistance is referred to as the on-state resistance Rdson.

Typically, MOSFET devices with low on-state resistance Rdson are preferred as they have higher current capability. However, it is well known that the breakdown voltage of MOSFET devices increases as the on-state resistance Rdson of the devices increases. Thus, there is a trade-off between reducing

Rdson and having a high enough break down voltage BVdss.

It is known that the on-state resistance Rdson may be decreased by increasing the packing density of a MOSFET device i.e. the number of base cells per cm ² . For example, a hexagonal MOSFET (HEXFET) device comprises a plurality of cells, each cell having a hexagonal polysilicon gate and source region

forming vertices of the hexagonal polysilicon gate, and has a high packing density e.g. 10 ⁵ hexagonal cells per cm ² . Usually, the smaller the size of the cells, the higher is the packing density and thus, the smaller the on-state resistance. Therefore, many improvements to MOSFET devices are aimed at reducing the size of the cells.

However, as the cell size is reduced, the channel length is reduced until a limit is reached when the depletion layer width of the body region becomes comparable to the channel length causing punch-through current at high drain biases which impacts the breakdown voltage BVdss and causes degradation to the threshold voltage. In other words, as the channel length is reduced to a critical limit, short-channel effects arise which complicate device operation and degrade device performance, such as reduced threshold and breakdown voltage. There is therefore a limit below which the cell size cannot be reduced or improvements need to be made to eliminate or minimise the short-channel effects. Different techniques have been developed to reduce Rdson whilst maintaining or increasing the breakdown voltage, increase the breakdown voltage capability whilst maintaining or reducing Rdson and to avoid a degradation of the threshold voltage and Undamped Inductive Switching (UIS) capability.

For example, in an attempt to reduce the on-state resistance Rdson of a MOSFET device whilst not impacting significantly the breakdown voltage of the device, it has been proposed to introduce multilayer structures in the epitaxial region of the device. These are known as super junction structures.

An article entitled ¹ A Novel High-Voltage Sustaining Structure with Buried Oppositely Doped Regions' by Xing Bi Chen, Xin Wang and Johnny K.O. Sin, in IEEE Transactions on Electron Devices, Vol. 47. No. 6, June 2000 describes a super junction structure having buried floating regions in the drift region of the MOSFET device connected together at the edge termination. In the case of p-type buried floating regions in a n-type drift region, due to the negative charges in the depleted p-type buried floating regions, a large part of the flux induced by the positive charges of the depleted n-drift region are terminated on the buried floating regions so that the electric field intensity is not allowed to accumulate throughout the entire thickness of the drift region. In other words, when the device is in an off

T/IB2007/001529

state, the potential drop is distributed uniformly in the drift region due to the charge balance across the uniformly distributed buried floating regions and with the result that the peak electric field which develops decreases allowing the voltage capability of the device to be increased. This means that a larger doping concentration can be used in the drift region without producing a high peak field. Since a larger doping concentration in the drift region can be used, the on-state resistance Rdson is reduced. Thus, by using buried floating regions, the resistivity of the drift region can be made smaller than that of a conventional MOSFET device with the same breakdown voltage and therefore, the on-state resistance Rdson can be reduced.

When the MOSFET device is turned on, the on-state resistance is momentarily high due to the drift region and the buried floating regions being fully depleted, and only a small current flows in the channel. In order to turn the device on fully (ie. unblock the device), the majority carriers in the buried floating regions and the drift region have to be recovered. A MOSFET is an unipolar or a majority carrier device and thus, when the channel is opened, electrons can be easily recovered for the n-type regions (e.g. the drift region) from the source. However, it is more difficult to recover holes for the p-type buried floating regions as a unipolar device cannot provide any holes to these regions. Thus, there is a delay between turning on a device and the device being fully on which delay depends on the time required to recover the majority charge carriers in the depleted regions. The delay characterises the response time of the MOSFET device. Ideally the aim when designing such super junction devices is to arrange for the delay to be zero or as close to zero as possible. US patent nos. 6,037,632 and 6,812,524 also disclose MOSFET devices having super junction structures.

US patent no. 6,037,632 describes a super junction MOSFET device having p-type buried regions in the active area of the device and large width p-type guard rings used with p-type buried resurf guard rings having a lower doping concentration in the termination area of the device. N+ regions are formed between the p-type buried regions in order to reduce Rdson by reducing the RJFET resistance between each p-type buried region.

PCT patent application WO 03/107432 describes a low on-state resistance power semiconductor device comprising a plurality of base cells with each base cell comprising a plurality of radially extending branches having source regions within body regions. At least one branch of each base cell extends towards at least one branch of an adjacent base cell and the body regions of the extending branches are merged together to form a single and substantially uniformly doped body or well region surrounding common drain regions in the epitaxial layer extending to the surface of the epitaxial layer. The branches extend from a central source region which surrounds a contact region which is electrically shorted to the source region. By having a uniform merged body region surrounding the source and contract region, the effects of the parasitic NPN or PNP bipolar transistor which appears in the source/body/common drain regions can be reduced (also known as snap back effect). This improves the breakdown voltage as well as the Undamped Inductive Switching (UIS). So this arrangement by increasing the cell or channel density, reduces the Rdson but with the arrangement of the branches and merged body region allows for the breakdown voltage capability to be maintained or improved.

Despite the number of different solutions that have been developed to improve the performance of a MOSFET device, there is a continuing need to develop solutions which further improve the dynamic and static behaviour of a power MOSFET device. Thus, there is therefore a need for an improved semiconductor device.

Summary

The present invention provides a semiconductor device and a method of forming a semiconductor device as described in the accompanying claims.

Brief description of the drawings

A semiconductor device and a method of forming a semiconductor device in accordance with the present disclosure will now be described, by way of example only, with reference to the accompanying drawings in which: FIG. 1 is a schematic cross-section diagram of a portion of a semiconductor device in accordance with the disclosure;

FIG. 2 is a graphical representation of the doping concentration profile and potential distribution profile across the line A-A shown in FIG. 1 ;

FIG. 3 is a graphical representation of the doping concentration profiles and potential distribution profile across the line B-B shown in FIG. 1 ; FIG. 4 is a top view of a plurality of base cells of a portion of a semiconductor device arrangement in accordance with an embodiment of the disclosure;

FIG. 5 is a top view of a plurality of base cells of a portion of a semiconductor device in accordance with another embodiment of the disclosure;

FIG. 6 is a schematic cross-section of the semiconductor device taken on the line A-A of FIG. 4;

FIG. 7 is a cross-sectional view of a real Scanning Capacitance Microscopy (SCM) picture of a portion of a semiconductor device in accordance with the disclosure; and

FIGs. 8-15 are schematic cross-section diagrams of the portion of the semiconductor device of FIG. 1 during different stages of fabrication.

Detailed description of the drawings

In the description that follows and in FIGs. 1-15, certain regions are identified as being of a particular material, conductivity and/or type. However, this is merely for convenience of explanation and not intended to be limiting. Those of skill in the art will understand based on the description given herein that various semiconductor materials can be used and that the doping of various regions of the device may be altered in order to obtain different device functions.

The present disclosure will be described with reference to a semiconductor device comprising a vertical semiconductor device such as a N-channel vertical MOSFET device. A vertical semiconductor device comprises a source electrode placed over the drain electrode which results in a current flow mainly in a vertical direction when the device is in the on state. It will be appreciated that the disclosure is not limited to vertical devices nor N-channel MOSFET devices and applies equally to other semiconductor devices, such as lateral devices, P-channel

vertical MOSFET devices or insulated gate bipolar transistor (IGBT) devices, or JFETs or diodes or similar devices.

Referring now to FIG. 1 , a semiconductor device in accordance with an embodiment of the disclosure comprises a N-channel vertical MOSFET device comprising a plurality of base cells. FIG. 1 and subsequent FIGs show a simplified cross-sectional view of only a portion of a base cell for simplicity.

The semiconductor device comprises a n-type semiconductor substrate 4 having a first surface and a second surface. A n-type epitaxial layer, comprising first 6, second 7 and third 8 epitaxial layers, is formed over the first surface of the semiconductor substrate 4. The doping concentration of the first 6, second 7 and third 8 epitaxial layers are less than the doping concentration of the semiconductor substrate 4. In an embodiment wherein the MOSFET device is capable of operating up to high voltages, for example in the order of 200 volts, the doping concentration of the first 6, second 7 and third 8 epitaxial layers is up to 2e15 cm ^'3 . P-type floating regions 10 (only two of which are shown) are formed in the n- type epitaxial layer comprising layers 6, 7 and 8 in the base cells. The p-type floating regions 10 are buried in the n-type epitaxial layers 6, 7 and 8 and are junction isolated from external source and drain electrodes. As shown in FIG. 1, the floating regions 10 in the first epitaxial layer 6 is are aligned vertically with corresponding floating regions 10 in the second epitaxial layer 7. In the embodiment shown in FIG. 1 and subsequent FIGs, the MOSFET device comprises two layers of floating regions 10 in first 6, second 7 and third 8 epitaxial layers. It will be appreciated that more than two layers of floating regions 10 can be used in additional epitaxial layers. The number of layers depends on the required breakdown voltage.

The p-type floating regions 10 in the epitaxial layers 6, 7 and 8 are separated from adjacent floating regions 10 in a lateral direction by a n-type separation region 12. The doping concentration of the n-type separation regions 12 is greater than the doping concentration of the first 6, second 7 and third 8 epitaxial layers. For example, the doping concentration of the n-type separation regions 12 may be around 1e16 cm ^"3 compared to a doping concentration of 2e15 cm ^'3 for the first 6, second 7 and third 8 epitaxial layers.

A p-type body region 14 extends from a first surface 16 of the third epitaxial layer 8 through the third epitaxial layer 8 typically to a depth of 1.5 microns. A n- type region 18 extends from the first surface 16 of the third epitaxial layer 8 into the p-type body region 14. The n-type region 18 is the current electrode region of the semiconductor device. In the embodiment shown in FIG. 1 , the n-type region 18 is the source region 18 of the MOSFET device and the semiconductor substrate 4 forms the drain region of the device. In the embodiment shown in FIG. 1 , an additional p-type region 20 extends into the p-type body region 14 from the first surface 16 of the third epitaxial layer 8 and so as to be adjacent the n-type region 18. The doping concentration of the additional p-type region 20 is greater than the doping concentration of the p-type body region 14. P-type region 20 improves contact with the source electrode and with the body region 14. The latter reduces the parasitic NPN bipolar action in the body region 14 and avoids vertical punch-through between the source region 18 and the third epitaxial layer 8. The p-type body region 14 forms a body-source PN junction 15 with the source region 18 and a body-epi junction 17 with the third epitaxial layer 8 both of which extend to the first surface 16. The part 21 of the third epitaxial layer 8 between the p-type body regions 14 and through which the current flows from the channel in the body region 14 to the drain region 4, when the device is in an on state, is called the active drain region 21 of the drift region and the body-epi junction 17 is also known as the body-drain junction.

The floating regions 10 are formed such that each floating region 10 has a greater vertical dimension than a lateral dimension. In other words, each floating region 10 has a greater width in a vertical direction than in a lateral direction, the lateral direction being parallel to the first surface 16 of the third epitaxial layer 8. Typically, the dimension of each floating region 10 is greater by 15 to 20% in the vertical direction than the lateral direction. In an embodiment, each floating region has a width in a vertical direction of 2-3 microns. This will be discussed in more detail below. In addition, the floating regions 10 are formed such that the distance 3 between the body region 14 and a floating region 10 in the third epitaxial layer 8 is such that the gain of the parasitic transistor device (e.g. the parasitic vertical PNP

bipolar transistor) between the body region 14 and the floating region 10 is maximised. This allows for the holes to be injected into the floating regions 10 when the MOSFET device is turned on to allow majority carriers in the floating regions to be recovered relatively quickly after being fully depleted without the need for an additional injector device. This ensures that the delay between turning on a device and the device being fully on, is kept to a minimum which improves the response time of the device. The gain of the parasitic transistor device will also depend on the net doping concentration of the third epitaxial layer 8 between the floating region 10 and the body region 14 due to the fact that the third epitaxial layer 8 forms the base electrode of the parasitic transistor device.

Thus, the distance 3 is selected such that the gain is maximised to maximise the charge injection on device turn on. The distance 3 may be in the range of 1-2 microns depending on the required breakdown voltage and will be shorter for a 200 volt MOSFET device compared to a 600 volt MOSFET device. It is expected that the gain will be greater than 10 and possibly 50 or 60 depending on the doping profiles, and required breakdown voltage.

For the same reasons, the distance 5 between floating regions 10 in adjacent epitaxial layers may also be arranged such that the gain of the parasitic transistor device (e.g. the parasitic vertical PNP bipolar transistor) between the floating regions 10 is maximised. With such an arrangement the MOSFET device comprises a plurality of spaced floating islands which improves the switching speed of the device.

In the embodiment shown in FIG. 1, a n-type pre-control region 19, which is referred to as a pre-gate implant (PGI) region, is formed in the third epitaxial layer 8 and extends from the first surface 16 of the third epitaxial layer 8 to a depth of 1 micron around part of the p-type body region 14. The PGI region 19 increases the n-type doping concentration in the third epitaxial layer 8 around the body region 14 compared to the rest of the third epitaxial layer 8. By having a higher doping concentration around the body region 14, the width of the current path from the source region 18 is increased and also the surface resistance component due to the JFET effect, known as RJFET, is reduced both of which results in Rdson being reduced. In addition, the PGI region 19 allows for the doping concentration at the

first surface 16 in the centre of the base cell to be reduced which allows for an increase in breakdown voltage and a reduction in the gate/drain capacitance Cgd. Furthermore, the PGI region 19 further suppresses lateral spread of the body region 14 during subsequent process steps which reduces RJFET between two body regions 14 and improves the breakdown voltage. However, in order to avoid penalising the breakdown voltage of the device, the PGI region typically does not extend deeper into the second epitaxial layer 8 than the p-type body region 14. Thus, the PGI region 19 improves the trade-off between Rdson and the breakdown voltage. A field oxide layer 22, having a typical thickness of 0.7 microns, extends over the first surface 16 of the third epitaxial layer 8 and a gate oxide layer 24 extends over the first surface 16 of the epitaxial layer 6 over a substantial part of the PGI region 19 body region 14. Gate oxide layer 24 typically comprises a silicon oxide layer having a thickness of 0.06 microns depending on the operating voltage. Thus, the gate oxide layer 24 extends over the body-source 15 and body-drain 17 junctions at the first surface 16 of the third epitaxial layer 8. An insulated gate region 26 is formed over gate oxide layer 24 and field oxide layer 22 and typically comprises a doped polycrystalline semiconductor material such as polysilicon. A dielectric layer 28 is formed over the insulated gate region 26. The dielectric layer 28 may comprise a silicon oxide layer or may comprise several layers, such as oxide/nitride/oxide layers.

In another embodiment, a n-type intermediate region 23 (shown in dotted lines) may extend between the PGI regions 19 of a base cell (only one PGI region 19 is shown in FIG. 1) under the field oxide layer 22. The doping concentration of the n-type intermediate region 23 is less than the doping concentration of the bulk of the third epitaxial layer 8. The lightly doped intermediate region 23 is a graded epitaxial layer arranged to be under the thicker field oxide layer 22 to avoid an increase in electric field in this area which helps to increase the breakdown voltage of the device. Having a 'terraced ¹ gate oxide layer with a thinner oxide layer over the body- source 15 and body-drain 17 junctions compared to the oxide layer over the active drain region 21 (or lightly doped intermediate region 23 if used) ensures that the

breakdown voltage is increased, reduces Cgd capacitance and improves device switching speeds. A method of making a semiconductor device with such a 'terraced' gate oxide layer is described in an article by Ueda et al. in IEEE Transactions of Electronic Devices, vol. ED-31 (no,.4):416-20 1984, entitled 'A new vertical double diffused MOSFET - the self-aligned terraced-gate MOSFET ¹ .

It will however be appreciated that instead of a 'terraced ¹ gate oxide layer, the gate region 26 may be formed on a typical gate oxide layer.

A metal or ohmic layer 30 is formed over the dielectric layer 28 and contacts the source region 18 to form the source electrode. A spacer 32 isolates the metal layer 30 from the insulated gate region 26.

A metal or ohmic layer 34 is formed over the second surface of the semiconductor substrate 4 to form the drain electrode.

Referring now to FIG. 2 which shows the doping profiles and potential distribution in the vertical direction in the centre of the base cell as indicated by line A-A on FIG. 1 , line 50 shows the doping profile for the n-type regions with points 51 corresponding to the peak doping of two separation regions 12, point 53 corresponding to the first epitaxial layer 6 and point 55 corresponding to the substrate.

Referring now to FIG. 3 which shows the doping profiles and potential distribution in the vertical direction through the middle of the additional p-type region 20 as indicated by line B-B on FIG. 1 , line 60 indicates the net doping profile over the cross section, line 62 shows the doping profile for the p-type regions, line 64 shows the doping profile for the n-type regions and line 66 shows the potential distribution at breakdown condition over the cross section. Points 61 correspond to the peak doping of two n-type separation regions 12, point 65 corresponds to the n-type PGI region 19, points 63 correspond to the peak doping of two floating regions 10, point 67 corresponds to the additional p-type region 20 and point 69 corresponds to the p-type body region 14. The method of forming the separation regions 12 and the floating regions 10, as described below, is arranged such that the peak doping profiles of the separation regions 12 and the floating regions 10 are aligned vertically (same depth) and symmetrical which results in the combined doping profile being symmetrical, as shown in FIG. 3. This ensures that

the potential profile, as indicated by line 66, is a smooth curve without any potential barriers (spikes) which would restrain carrier injection during switching. A smooth potential distribution provides for uniform injection of charges which results in improved device response on switching. As discussed above, the MOSFET device comprises a plurality of base cells.

In an embodiment, each base cell has a configuration as set out in FIGs. 4-6. FIG. 4 shows a top view of a plurality of base cells during manufacture and before a body region 14 merge operation, like features to those referred to above with respect to FIGs. 1-3 are referred to be the same reference number. In order to provide a more complete view of the structure beneath the insulated gate region 26, a middle portion 33 without the insulated gate region 26 is shown. FIG. 5 shows a top view of a plurality of base cells in accordance with an alternative configuration during manufacture and after a body region 14 merge operation, like features to those referred to above with respect to FIGs. 1-4 are referred to be the same reference number. FIG. 6 is a cross-sectional view of a portion of the MOSFET device taken along lines A-A of FIG. 4 after a body region merge operation.

Each base cell has a source region 18 arranged as four branches 80 extending from a central portion of the source region 18 in which the additional p- type region 20 is centred. The source region 18 is formed in the body region 14 and thus, the branches 80 include the source region 18 within the body region 14. The body-source junction 15 and the body-drain junction 17 are shown in FIGs. 4 and 5. The active drain region 21 is formed between the body regions 14. The adjacent base cells are aligned such that at least one branch 80 of a base cell extends towards a branch 80 of an adjacent base cell. The body regions 14 of adjacent cells at the end of these branches are merged to each other by diffusion, for example by a thermal operation, of the adjacent body regions 14 at the ends of the branches 80 as more clearly shown in FIG. 6.

Since the body regions 14 of adjacent base cells are merged, a continuous substantially uniformly doped body region is formed which ensures that the parasitic bipolar transistor phenomenon which appears in the source/body/active drain structure is avoided since the base region will always be polarised with an

uniform potential. Thus, the breakdown voltage is improved as well as the UIS behaviour.

In an embodiment, not shown in FIGs. 4-6, the floating regions 10 may be configured to have a lateral shape similar to the source 18 and body 14 regions before a merge operation: that is, to comprise branches buried in the epitaxial layers 6 and 8 below the body region 14 having a shape such as the branches 80 shown in FIGs. 4 or 5. An example of such an arrangement is shown in FIG. 7.

Due to the separation regions 12 between the floating regions, the floating regions have an elliptical shape, with a greater dimension in the vertical direction compared to the lateral direction.

In the configuration shown in FIG. 4, each base cell comprises four branches 80 extending orthogonally in straight lines and are linked to each other by four straight links 41. However, alternatively these branches may have non-linear or undulating shape, such as a zig-zag shape or there may be less or more than four branches or the branches extend at different angles or the branches 80 may be linked by concave curving links 43 as shown in FIG. 5. By having concave curving links 43 as shown in FIG. 5, the body-source junction 15 is rounded and concave and the body-drain junction 17 is generally ring-shaped which improves the device breakdown voltage capability by reducing electric field at the concave PN junctions. Having concave branched-shape floating regions also helps to increase the breakdown voltage capability for the same reasons.

In an embodiment, the base 14 and source 18 regions are formed after the insulated gate region 26 has been formed. The branches 80 are defined by patterning and etching the insulated gate region 26. More details of the configurations shown in FIGs. 4-6 and the method of manufacture can be found in PCT patent application nos. WO 03/107432 and WO 2006/024322.

Alternative configurations of the base cell and/or the floating regions may also be used and it is not intended that the invention be limited to the specific configuration disclosed herein. For example, the floating regions may be formed having different configurations such as stripes, dots, mesh shapes, cross shapes or any combination thereof.

A method of forming a semiconductor device in accordance with an embodiment of the present disclosure will now be described with reference to FIGs. 8-15. Only part of the semiconductor device is shown for simplicity.

As shown in FIG. 8, a first n-type epitaxial layer 6 is grown on an n-type substrate 4. The doping concentration of the n-type substrate 4 is greater than the doping concentration of the first epitaxial layer 6. An oxide layer 70, such as a silicon oxide layer, is formed over the first epitaxial layer 6. A mask layer 72 is then formed over the first epitaxial layer 6. An opening 74 is formed in the mask layer 72. Floating region 10 is then formed within the first epitaxial layer 6 by implantation or diffusion of a p-type material, such as boron (B11+), in the first epitaxial layer 6 through the opening 74.

The layout of the mask layer 72 is arranged so that the shape of the floating regions 10 can be one of stripes, dots, mesh shapes, cross-shapes or any combination thereof depending on the configuration of the device.

After the floating regions 10 are formed in the first epitaxial layer 6, the mask layer 72 is removed and separation regions 12 are formed by a blanket implant of n-type material, such as phosphorous or arsenic, in the first epitaxial layer 6 as shown in FIG. 9. The oxide layer 70 is then removed and a second epitaxial layer 7 is grown over the floating regions 10 as shown in FIG. 10.

An oxide layer 71 , such as a silicon oxide layer, is formed over the second epitaxial layer 7 and a mask layer 73, having the same configuration as mask layer 72, is then formed over the second epitaxial layer 7. An opening 75 is formed in the mask layer 73. Floating region 10 is then formed within the second epitaxial layer 7 by implantation or diffusion of a p-type material, such as boron (B11+), in the second epitaxial layer 7 through the opening 75.

After the floating regions 10 are formed in the second epitaxial layer 7, the mask layer 73 is removed and separation regions 12 are formed by a blanket implant of n-type material, such as phosphorous or arsenic, in the second epitaxial layer 7 as shown in FIG. 11.

Then, a third epitaxial layer 8 is grown.

A dielectric layer 22, such as a silicon oxide layer, is then formed over the device as shown in FIG. 12. An opening 76 is made through the dielectric layer 22 (the field oxide layer 22) by way of patterning and etching and a dielectric layer 24, the gate oxide layer 24, is grown on the third epitaxial layer 8 in the opening 76. The PGI region 19 is then formed in the third epitaxial layer 8 by a blanket implant of n-type material, such as arsenic or phosphorous, into the third epitaxial layer 8 through the opening 76. The doping does of the n-type material is in the range of 1-3e12cm ^"2 . Since the PGI region 19 is formed through the opening 76 defined by the thicker field oxide layer 22, the result is that the thinner gate oxide layer 24 extends over a substantial part of the PGI region 19 and the thicker field oxide layer 22 extends over the active drain region 21 of the third epitaxial layer 8 (between the PGI regions 19).

After implanting the PGI region 19, the device is subject to a high temperature thermal drive operation in which the PGI region 19, floating regions 10 and separation regions 12 diffuse through the first 6, second 7 and third 8 epitaxial layers.

In an embodiment of the MOSFET device in accordance with the disclosure which includes a n-type intermediate lightly doped region 23 at the surface of the third epitaxial layer 8 between the PGI regions 19, the intermediate region 23 is formed by reducing the doping concentration in the third epitaxial layer 8 during the final stages of growing the third epitaxial layer 8 so as to provide a layer of reduced doping concentration at the surface 16 of the third epitaxial layer 8 which remains as intermediate region 23 after the source 18, body 14 and PGI 19 regions are formed in the third epitaxial layer 8. For simplicity, the lightly doped layer 23 at the surface of the third epitaxial layer 8 is not shown in the FIGs.

In FIG. 13, a polysilicon layer 26, or other type of conductive layer, is then formed over the gate oxide layer 24 and the field oxide layer 22, for example, by deposition and doped with a high dose n-type implantation. A dielectric layer 28 is then deposited over the polysilicon layer 26. The dielectric layer 28 may comprise a silicon oxide or TEOS layer or may comprise several layers, such as oxide/nitride/oxide layers.

The dielectric layer 28 and the polysilicon layer 26 are then etched to provide a body opening 78 through which p-type material, such as boron (B11+), is implanted in order to form the body region 14. The etched polysilicon layer 26 forms the insulated gate region 26 of the MOSFET device. The wafer is then subjected to a high temperature thermal drive operation, for example around 1080 ⁰ C, to drive the p-type body region 14 into the second epitaxial layer 8.

The n-type separation regions 12 compensate for the lateral spread of the floating regions 10 during the high temperature thermal drive operations: in other words, from the net doping value perspective in a lateral direction, which is the difference between the p-type and n-type dopingJnJheJateπaLdmction _^ the-±iigbeL. n-type doping of the separation regions 12 compensates for the adjacent p-type doping of the floating regions 10. This means that the RJFET is reduced which reduces Rdson. Since the lateral spread is compensated for by the n-type separation regions 12, longer drive operations can be used to drive the floating regions 10 to achieve the optimum distance 3 between the body region 14 and adjacent floating region and the optimum distance 5 between adjacent floating regions 10. As discussed above, the optimum distances 3 and 5 are chosen to maximise the gain of the parasitic transistor device to improve device switching speeds. A mask 82 is formed over a portion of the second epitaxial layer 8 to mask off part of the body opening 78 and leave an opening 84 as shown in FIG. 14. The source region 18 is then formed by implantation of a n-type material, such as arsenic or phosphorus, into the second epitaxial layer 8 through the opening 84. Since the body region 14 and the source region 18 are all implanted through the openings 78 and 84 which are defined by the insulated gate region 26, the source region 18, and the body region 14 are self-aligned.

Referring now to FIG. 15, a dielectric layer (not shown), such as a TEOS layer, is formed over the second epitaxial layer 8 in the body opening 78. This dielectric layer (not shown) is then etched to provide a spacer 32 and opening 86, through which p-type material is implanted to form the additional p-type region 20. Preferably, the implant step comprises implanting a p-type material, such as born (B 11 +), having a doping dose of about 5e15 cm ^"2 .

The partly processed semiconductor device is then subjected to a low thermal operation and short drive so as to drive the source region 18, body region

14, and additional p-type region 20 into the third epitaxial layer 8. For example, the semiconductor device is annealed up to a temperature of 900-950°C for 30 minutes. Other process steps then take place including metallization wherein a metal layer 30 is formed on the dielectric layer 28 in contact with the source region

18 and additional p-type region 20 so as to provide the source electrode, and a metal layer 34 is formed over the second surface of the semiconductor substrate 4 to form the drain electrode as shown in FIG. 1. The spacer 32 isolates the source electrode 30 from the insulated gate region 26.

In summary, the present invention provides an improved semiconductor device that has floating regions separated in the lateral direction by separation regions which ensure that the lateral spread of the floating regions is compensated. The floating regions can thus be formed having a greater dimension in the vertical direction than the lateral direction which makes it possible to achieve the optimum distance between the body region and the floating regions and between the floating regions themselves such that the gain of the parasitic transistor device between the regions is maximised. Ensuring a maximum gain of the parasitic transistor device helps to provide efficient carrier injection during the turning on of the MOSFET device without the need to have additional injector devices or a large number of layers of floating regions (e.g. 2 or 3 layers compared to 5 or 6 for known super junction structures) or interconnected floating regions, all of which impact the trade-off between Rdson and the breakdown voltage and device cost. In addition, the separation regions allow for the doping concentration of the epitaxial layers to be less than typical devices which increases the breakdown voltage capability but as the separation regions decrease RJFET, there is no degradation to Rdson.

No additional masks are required to form the separation regions and thus, there is no significant increase in manufacturing costs. Moreover, a MOSFET device comprising a plurality of base cells, each base cell comprising the following combination of features described above, floating islands 10 with separation regions 12 therebetween and spaced in order to

maximise the gain of the parasitic transistor device, PGI regions 19 at the surface 16, lightly doped intermediate regions 23 between the PGI regions at the surface, a terraced gate oxide layer 22, the branched configuration for the source 18, body 14 and floating regions 10, has significantly improved device performance compared to the known MOSFET devices having super junction structures and standard vertical MOSFET devices. For example, such a combination improves significantly the dynamic response time of a MOSFET device, decreases Rdson by about 45% with respect to known super junction structures and 70% with respect to standard (not super junction structures) vertical MOSFET devices, for the same breakdown voltage.