SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

WIPO Patent Application WO/2023/157048

A1

In the present invention, a first insulating layer 1 is on a substrate 40, a first metal wiring layer 2 and a fourth metal wiring layer 3 are embedded in the insulating layer, a second metal wiring layer 4 abuts the metal wiring layer 2 and extends perpendicularly thereto, a first impurity layer (n+ layer) 5a abuts the second metal wiring layer 4 and extends perpendicularly thereto, a semiconductor p layer 6 and a second impurity layer (n+ layer) 5b abut the first impurity layer 5a and extend perpendicularly thereto, side surfaces of the first impurity layer 5a, the semiconductor p layer 6, and the second impurity layer 5b are partially covered by a first gate insulating layer 7, a first gate conductor layer 8 abuts the first gate insulating layer 7, the second impurity layer 5b is covered by a second insulating layer 9, and the n+ layer 5b is connected with a third metal wiring layer 10 via a contact hole 33. The fourth metal wiring layer 3 is connected to the gate conductor layer 8.

KAKUMU MASAKAZU (JP)
HARADA NOZOMU (JP)

PCT/JP2022/005810

August 24, 2023

February 15, 2022

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UNISANTIS ELECT SINGAPORE PTE (SG)
KAKUMU MASAKAZU (JP)
HARADA NOZOMU (JP)

H01L29/78

WO2018203181A1

2018-11-08

JP2004128182A	2004-04-22
JP2005268438A	2005-09-29
JP2009164589A	2009-07-23
US20050282356A1	2005-12-22
JP2005101141A	2005-04-14
JPH03225873A	1991-10-04
JP2020535642A	2020-12-03
JP2009123882A	2009-06-04
JP2004349291A	2004-12-09
JP2008205168A	2008-09-04
JPH05326952A	1993-12-10
JPS6245058A	1987-02-27

TANAKA Shinichiro et al. (JP)

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