Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/152586
Kind Code:
A1
Abstract:
Provided is a semiconductor device that is configured to allow miniaturization and high integration. This semiconductor device includes a memory cell including first to third transistors and a capacitor. The first to third transistors each have a metal oxide with a side surface thereof being covered by a source electrode and a drain electrode. The second and third transistors share the metal oxide. The capacitor is provided above the first to third transistors. An electroconductor having a region that functions as a write bit line is provided so as to have a region that is in contact with an upper surface and side surface of one of a source electrode and drain electrode of the first transistor. An electroconductor having a region that functions as a read bit line is provided so as to have a region that is in contact with an upper surface and side surface of one of a source electrode and a drain electrode of the third transistor. The other of the source electrode and the drain electrode of the first transistor, and a gate of the second transistor are electrically connected to one electrode of the capacitor.
Inventors:
YAMAZAKI SHUNPEI (JP)
ONUKI TATSUYA (JP)
KATO KIYOSHI (JP)
KUNITAKE HITOSHI (JP)
HODO RYOTA (JP)
ONUKI TATSUYA (JP)
KATO KIYOSHI (JP)
KUNITAKE HITOSHI (JP)
HODO RYOTA (JP)
Application Number:
PCT/IB2023/050698
Publication Date:
August 17, 2023
Filing Date:
January 27, 2023
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
H10B12/00; G11C11/405; H01L29/786; H10B41/70; H10B99/00
Domestic Patent References:
| WO2020201865A1 | 2020-10-08 | |||
| WO2018220471A1 | 2018-12-06 | |||
| WO2020157553A1 | 2020-08-06 | |||
| WO2020008304A1 | 2020-01-09 |
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