Title:
SEMICONDUCTOR DEVICE AND MULTI-CHIP MODULE
Document Type and Number:
WIPO Patent Application WO/2016/170678
Kind Code:
A1
Abstract:
The present invention addresses the problem of providing a semiconductor inspection circuit capable of connection state testing for, for example, a power supply, ground, or signal bump, in a product operation state in a semiconductor package or printed circuit board equipped with semiconductor LSI. The means for addressing this problem has a route-switchable circuit in a driver/receiver input unit and a mechanism capable of conveying output from a route switching circuit near a receiver circuit to a voltage waveform circuit with built-in variable termination, monitors the DC level at a termination having a fixed DC resistance during signal bump connection state observation, inputs a step wave during I/O power supply bump connection state observation, observes the resulting response waveform, and thereby makes it possible to observe a bump break condition in a product operation state.
Inventors:
UEMATSU YUTAKA (JP)
OOSAKA HIDEKI (JP)
TOBA TADANOBU (JP)
SHIMBO KENICHI (JP)
OOSAKA HIDEKI (JP)
TOBA TADANOBU (JP)
SHIMBO KENICHI (JP)
Application Number:
PCT/JP2015/062514
Publication Date:
October 27, 2016
Filing Date:
April 24, 2015
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G01R31/02; G01R31/28
Foreign References:
| JPH063400A | 1994-01-11 | |||
| JP2011080808A | 2011-04-21 | |||
| JP2007017229A | 2007-01-25 | |||
| JP2009210369A | 2009-09-17 | |||
| JP2006138844A | 2006-06-01 |
Attorney, Agent or Firm:
SEIRYO I. P. C. (JP)
青稜 patent business corporation (JP)
青稜 patent business corporation (JP)
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