Title:
SEMICONDUCTOR DEVICE FOR POWER AMPLIFICATION
Document Type and Number:
WIPO Patent Application WO/2023/188971
Kind Code:
A1
Abstract:
A semiconductor device (1) for power amplification comprises: a substrate (10); a lower surface electrode (64); a semiconductor layer (20); a source electrode (60); a drain electrode (50); a gate electrode (40); and a field plate (80). The semiconductor layer (20) is partitioned into active regions (31) and element separation regions (30). A channel region is composed of a plurality of unit channel regions (90) divided by the element separation regions (30) and arranged side by side in the Y-axis direction in a plan view. The source electrode (60) is composed of a plurality of unit source electrodes facing the respective unit channel regions (90). The field plate (80) is composed of a plurality of unit plates (81) facing the respective unit channel regions (90). A plurality of plate driving lines (82) extend in the X-axis direction and electrically connect the plurality of unit source electrodes and the plurality of unit plates (81). At least one of the plate driving lines (82) is provided to each of the unit plates (81) in the range of the element separation regions (30).
Inventors:
KAWASHIMA KATSUHIKO
SENSHU YOSHITERU
KANDA YUSUKE
MOTOYOSHI KANAME
SENSHU YOSHITERU
KANDA YUSUKE
MOTOYOSHI KANAME
Application Number:
PCT/JP2023/005731
Publication Date:
October 05, 2023
Filing Date:
February 17, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
H01L29/778; H01L21/338; H01L29/812
Domestic Patent References:
| WO2012063329A1 | 2012-05-18 |
Foreign References:
| JPH10144913A | 1998-05-29 | |||
| JP2020027912A | 2020-02-20 | |||
| JP2022016950A | 2022-01-25 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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