Title:
SEMICONDUCTOR DEVICE PRODUCTION METHOD AND STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/053521
Kind Code:
A1
Abstract:
This semiconductor device production method is for preparing a structure 200 including: an interposer 60 divided into a plurality of installation areas 65 by groove sections 61 formed therein; and semiconductor elements 202a, 202b arranged on the individual installation areas 65. The semiconductor element 202a is a processor, and the semiconductor element 202a is memory. Each of the groove sections 61 includes two parallel grooves 61a. The semiconductor elements 202a, 202b are sealed in the structure 200 so that a sealing material 80b enters into each of the grooves 61a. The rear surface of the interposer 60 is polished so as to expose the sealing material 80b that has entered into each of the grooves 61a. The sealing material 80b is subsequently cut along the groove sections 61 and a plurality of semiconductor devices 201 are obtained. This method makes it possible to eliminate blade changes and improve production efficiency because only the sealing material 80b is cut when dividing into individual pieces.
Inventors:
AOYAMA MOTOO (JP)
HATAKEYAMA KEIICHI (JP)
IMAZU YUKI (JP)
HATAKEYAMA KEIICHI (JP)
IMAZU YUKI (JP)
Application Number:
PCT/JP2023/031628
Publication Date:
March 14, 2024
Filing Date:
August 30, 2023
Export Citation:
Assignee:
RESONAC CORP (JP)
International Classes:
H01L23/12; H01L21/301; H01L25/04; H01L25/18
Foreign References:
| JP2016058655A | 2016-04-21 | |||
| JP2011119324A | 2011-06-16 | |||
| US20060189099A1 | 2006-08-24 | |||
| JP2009272492A | 2009-11-19 | |||
| US20170053859A1 | 2017-02-23 | |||
| US20210202436A1 | 2021-07-01 | |||
| JP2007194469A | 2007-08-02 |
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
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