SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2015/079756

A1

This semiconductor device (100) is provided, on a substrate, with: a plurality of oxide semiconductor TFTs, each of which comprises a first gate electrode (12), a first insulating layer (20) that is in contact with the first gate electrode, an oxide semiconductor layer (16) that is arranged so as to face the first gate electrode with the first insulating layer being interposed therebetween, and a source electrode (14) and a drain electrode (15) that are connected to the oxide semiconductor layer; and an organic insulating layer (24) which covers only some of the plurality of oxide semiconductor TFTs. The plurality of oxide semiconductor TFTs include a first TFT (5A) that is covered by the organic insulating layer and a second TFT (5B) that is not covered by the organic insulating layer. The second TFT is provided with a second gate electrode (17) which is arranged so as to face the oxide semiconductor layer with a second insulating layer (22) being interposed therebetween, and the second gate electrode (17) is arranged so as to overlap at least a part of the first gate electrode with the oxide semiconductor layer lying therebetween when viewed from the normal direction of the substrate.

SAITOH TAKAO
KANEKO SEIJI
KANZAKI YOHSUKE
TAKAMARU YUTAKA
IDE KEISUKE
MATSUO TAKUYA
MORI SHIGEYASU
MATSUKIZONO HIROSHI

PCT/JP2014/072298

June 04, 2015

August 26, 2014

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SHARP KK (JP)

H01L29/786; H01L21/28; H01L21/283; H01L21/336

WO2012032749A1

2012-03-15

JP2012084572A	2012-04-26
JP2010021555A	2010-01-28
JP2013149995A	2013-08-01
JP2009277478A	2009-11-26
JP2013041945A	2013-02-28

OKUDA SEIJI (JP)
Seiji Okuda (JP)

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