SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2015/098246

A1

Disclosed is a technique which is capable of suppressing deterioration of an insulating layer in a termination region. This semiconductor device (100) comprises a semiconductor substrate (10) that is provided with an element region (110) and a termination region (120) that surrounds the element region (110). The element region (110) comprises, a gate trench (20), a gate insulating film (22) that covers the inner surface of the gate trench (20), and a gate electrode (24) that is arranged inside the gate insulating film (22). The termination region (120) comprises a plurality of termination trenches (30a-30j) which are formed around the element region (110), and buried insulating layers (32b-32e) which are respectively arranged inside the plurality of termination trenches (30a-30j). The buried insulating layer (32b) is formed also on the upper surface of the semiconductor substrate (10). An interlayer insulating film (40) is formed on the upper surface of the semiconductor substrate (10). A gate wiring line (44) is formed above the buried insulating layer (32b), but is not formed above the buried insulating layers (32c-32e).

SOENO AKITAKA (JP)
FUKUOKA YUJI (JP)

PCT/JP2014/077497

July 02, 2015

October 16, 2014

Click for automatic bibliography generation  

TOYOTA MOTOR CO LTD (JP)
SOENO AKITAKA (JP)
FUKUOKA YUJI (JP)

H01L21/336; H01L29/78; H01L29/06; H01L29/12

JP2013033931A	2013-02-14
JP2010135677A	2010-06-17
JP2005286042A	2005-10-13
JP2005502204A	2005-01-20

KAI-U PATENT LAW FIRM (JP)
Patent business corporation KAI-U Patent Law Firm (JP)

View/Download PDF      PDF Help

Previous Patent: SCISSORS

Next Patent: COMMUNICATION SYSTEM, COMMUNICATION TERMINAL, SERVER, COMMUNICATION METHOD, RECORDING MEDIUM, INFORM...