Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2015/141327
Kind Code:
A1
Abstract:
In an active region, a MOS gate structure of a trench gate type is provided on the substrate top side and a floating p-type region (9) is provided in a mesa region between trenches (2). A groove (10) is provided in a surface layer on the substrate top side of the floating p-type region (9), apart from the trenches (2). Inside the groove (10), a second gate electrode (12) is provided through an insulating layer (11) such as, for example, LOCOS. The second gate electrode (12) covers the surface on the substrate top side of the floating p-type region (9). That is, the second gate electrode (12) is disposed between the floating p-type region (9) and an interlayer insulating film (8) so as to be buried in the surface layer on the substrate top side of the floating p-type region (9), so that the substrate front surface is planarized. This makes it possible to enhance the controllability of turn-on di/dt, reduce the Miller capacity, and form a fine pattern element structure.
Inventors:
ONOZAWA YUICHI (JP)
TAMURA TAKAHIRO (JP)
TAMURA TAKAHIRO (JP)
Application Number:
PCT/JP2015/053492
Publication Date:
September 24, 2015
Filing Date:
February 09, 2015
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L29/78; H01L21/336; H01L29/41; H01L29/417; H01L29/739
Domestic Patent References:
| WO2013080806A1 | 2013-06-06 |
Foreign References:
| JP2011204803A | 2011-10-13 |
Attorney, Agent or Firm:
SAKAI, AKINORI (JP)
Akinori Sakai (JP)
Akinori Sakai (JP)
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