Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/149225
Kind Code:
A1
Abstract:
This semiconductor device comprises an insulating substrate, a plurality of wiring layers, a plurality of heat dissipation layers, a semiconductor element, and a sealing resin. Each of the plurality of wiring layers has a first principal surface and a first rear surface facing opposite each other in the thickness direction of the insulating substrate. The first rear surface of each of the plurality of wiring layers is joined to the insulating substrate. Each of the plurality of heat dissipation layers has a second principal surface facing the same side as the first principal surface in the thickness direction, and a second rear surface facing the side opposite to the second principal surface. The plurality of heat dissipation layers are positioned on the side opposite to the plurality of wiring layers with respect to the insulating substrate in the thickness direction. The second principal surface of each of the plurality of heat dissipation layers is joined to the insulating substrate. The semiconductor element is joined to one of the first principal surfaces of the plurality of wiring layers. The sealing resin covers the insulating substrate, the plurality of wiring layers, and the semiconductor element. Seen along the thickness direction, the plurality of wiring layers individually overlap on the plurality of heat dissipation layers.
Inventors:
KANDA TAKUMI (JP)
Application Number:
PCT/JP2020/000612
Publication Date:
July 23, 2020
Filing Date:
January 10, 2020
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
H01L23/36; H01L23/12; H01L25/07; H01L25/18
Domestic Patent References:
| WO2009131217A1 | 2009-10-29 |
Foreign References:
| JP2003031718A | 2003-01-31 | |||
| JP2001332823A | 2001-11-30 | |||
| JP2003100966A | 2003-04-04 | |||
| JP2002343911A | 2002-11-29 |
Attorney, Agent or Firm:
USUI Takashi et al. (JP)
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