Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/213133
Kind Code:
A1
Abstract:
This semiconductor device is provided with a wiring layer (16) patterned on a substrate 1 and including seed layers (2, 3), and an electroless plating layer (17) covering an upper surface and a side surface of the wiring layer (16). A layer-structured pattern including the wiring layer (16) and the electroless plating layer (17) includes at least one first region (21) in which a connection point of solder is formed, and at least one second region (22) which is formed so as to surround the at least one first region (21) with a gap from the first region (21).
Inventors:
HIRANO HIROSHIGE (JP)
ITO YUTAKA (JP)
ITO YUTAKA (JP)
Application Number:
PCT/JP2019/016671
Publication Date:
October 22, 2020
Filing Date:
April 18, 2019
Export Citation:
Assignee:
TOWERJAZZ PANASONIC SEMICONDUCTOR CO LTD (JP)
International Classes:
H01L21/60
Foreign References:
| JP2008277580A | 2008-11-13 | |||
| JP2010056136A | 2010-03-11 | |||
| JP2013118216A | 2013-06-13 | |||
| JP2009071066A | 2009-04-02 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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