Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/210170
Kind Code:
A1
Abstract:
The purpose of the present invention is to suppress the occurrence of wire breakage. A wiring portion (63) includes a vertical portion (64), a parallel portion (65), and an inclined portion (66). A lower end portion of the vertical portion (64) is connected to a chip bonding portion (61), and an upper end portion of the vertical portion (64) rises vertically upward relative to the chip bonding portion (61). The parallel portion (65) is connected to the upper end portion of the vertical portion (64) and is formed parallel with wiring boards (43b, 43d) and a semiconductor chip (50c) from said upper end portion. The inclined portion (66) is inclined from the parallel portion (65) toward a wiring bonding portion (62). Even when a wire (71b) is bonded to an obverse surface of the parallel portion (65) of the wiring portion (63) included in such a lead frame (60), the occurrence of deformation of the parallel portion (65) toward an insulated-circuit-board (40) side is suppressed.
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Inventors:
KATO RYOICHI (JP)
HINATA YUICHIRO (JP)
MURATA YUMA (JP)
HINATA YUICHIRO (JP)
MURATA YUMA (JP)
Application Number:
PCT/JP2023/008664
Publication Date:
November 02, 2023
Filing Date:
March 07, 2023
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L21/60; H01L23/48; H01L25/07; H01L25/18
Foreign References:
| JP2007288075A | 2007-11-01 | |||
| JP2019075524A | 2019-05-16 | |||
| JP7028391B1 | 2022-03-02 |
Attorney, Agent or Firm:
FUSO INTERNATIONAL PATENT FIRM (JP)
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