Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR PACKAGE STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2020/066797
Kind Code:
A1
Abstract:
Provided is a novel power wiring structure for effectively supplying power in a semiconductor integrated circuit device in which semiconductor chips are laminated. A first semiconductor chip (101) is laminated on a second semiconductor chip (102). A first power wiring (13) of the first semiconductor chip (101) is connected to second power wirings (31, 33) of the second semiconductor chip (102) through a plurality of first vias (21). The extending direction of the first power wiring (13) and that of the second power wirings (31, 33) are orthogonal to each other.
Inventors:
OKAMOTO ATSUSHI (JP)
TAKENO HIROTAKA (JP)
WANG WENZHEN (JP)
TAKENO HIROTAKA (JP)
WANG WENZHEN (JP)
Application Number:
PCT/JP2019/036598
Publication Date:
April 02, 2020
Filing Date:
September 18, 2019
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/82; H01L21/822; H01L25/065; H01L25/07; H01L25/18; H01L27/00; H01L27/04
Domestic Patent References:
| WO2013168354A1 | 2013-11-14 |
Foreign References:
| JP2012178425A | 2012-09-13 | |||
| JP2011082524A | 2011-04-21 | |||
| US20190252353A1 | 2019-08-15 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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