Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2004/036433
Kind Code:
A1
Abstract:
A CPU core (6) writes encode effective bit in a data register (12). A bit shift&sol total control unit (13) writes the effective bit indicated in the address in the data into a secondary data buffer register (13a). When data accumulation in the secondary data buffer register (13a) is FULL, the data stored in the secondary data buffer register (13a) is written into a memory (10). When this processing is repeated, and the total of the transfer bit reaches the upper limit of the memory (10), the CPU core (6) transfers all the contents in the memory (10) to a main memory (3). Since the CPU core (6) can read the data of variable−length code in one access, the processing performance of the encoder can be improved. A data accelerator realizes high performance by the operation substantially opposite thereto.
Inventors:
ISHIWATARI KAZUYOSHI (JP)
KUMAGAI MICHI (JP)
SAHO AKIKO (JP)
KUMAGAI MICHI (JP)
SAHO AKIKO (JP)
Application Number:
PCT/JP2002/010879
Publication Date:
April 29, 2004
Filing Date:
October 21, 2002
Export Citation:
Assignee:
RENESAS THCHNOLOGY CORP (JP)
ISHIWATARI KAZUYOSHI (JP)
KUMAGAI MICHI (JP)
SAHO AKIKO (JP)
ISHIWATARI KAZUYOSHI (JP)
KUMAGAI MICHI (JP)
SAHO AKIKO (JP)
International Classes:
G06F9/308; G06F9/312; (IPC1-7): G06F12/04; H03M7/40
Foreign References:
| JP2002009625A | 2002-01-11 | |||
| JPH04333921A | 1992-11-20 | |||
| JPH11184750A | 1999-07-09 | |||
| JPH07182230A | 1995-07-21 | |||
| JPH08221248A | 1996-08-30 |
Attorney, Agent or Firm:
Tsutsui, Yamato (3F Azeria Bldg., 1-1, Nishi-shinjuku 8-chom, Shinjuku-ku Tokyo, JP)
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