SEMICONDUCTOR INTEGRATED CIRCUIT

Title:

SEMICONDUCTOR INTEGRATED CIRCUIT

Document Type and Number:

WIPO Patent Application WO/2011/027499

Kind Code:

A1

Abstract:

Disclosed is a semiconductor integrated circuit (1) wherein memory macro (10) has: a plurality of memory cells (10A-10D) arranged in matrix; a plurality of word lines (WL1, WL2), each of which corresponds to each row of the memory cells (10A-10D); and a plurality of word line drivers (12A, 12B) that drive the word lines (WL1, WL2), respectively. In the semiconductor integrated circuit, voltages of the word lines (WL1, WL2) are set at different levels, depending on the threshold voltage characteristics of a Pch transistor (31A) and those of an Nch transistor (31B), when the word lines (WL1, WL2) are in an active state.

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Inventors:

SUMITANI NORIHIKO
TERANO TOSHIO

Application Number:

PCT/JP2010/004259

Publication Date:

March 10, 2011

Filing Date:

June 28, 2010

Export Citation:

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Assignee:

PANASONIC CORP (JP)
SUMITANI NORIHIKO
TERANO TOSHIO

International Classes:

G11C11/413; G11C11/41; G11C11/418

Foreign References:

JP2008262637A	2008-10-30
JP2008065968A	2008-03-21
JP2006127669A	2006-05-18
JP2008047180A	2008-02-28
JP2008004259A	2008-01-10
JPH11232878A	1999-08-27