Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/142546
Kind Code:
A1
Abstract:
This semiconductor integrated circuit is provided with: a first flip-flop (1a) provided with a first slave latch; a second flip-flop (2a) provided with a second slave latch; and a clock generation circuit (3) that supplies a common clock signal to the first flip-flop (1a) and the second flip-flop (2a), wherein the first slave latch comprises a first inverter (I14), a first feedback inverter (I15) to which an output signal from the first inverter (I14) is inputted, and a first switch (S13) connected between an input terminal of the first inverter (I14) and an output terminal of the first feedback inverter (I15), and an output signal of the first flip-flop (1a) is outputted from the output terminal of the first feedback inverter (I15).
Inventors:
NAKANISHI KAZUYUKI
Application Number:
PCT/JP2018/045448
Publication Date:
July 25, 2019
Filing Date:
December 11, 2018
Export Citation:
Assignee:
PANASONIC IP MAN CO LTD (JP)
International Classes:
H03K3/037; G01R31/28; H03K3/3562
Foreign References:
| JP2017096881A | 2017-06-01 | |||
| JPH0621777A | 1994-01-28 | |||
| JPH05325586A | 1993-12-10 | |||
| JP2017055332A | 2017-03-16 | |||
| JP2003043108A | 2003-02-13 | |||
| JP2006005661A | 2006-01-05 | |||
| JP2009021650A | 2009-01-29 | |||
| JPH07131302A | 1995-05-19 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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