Title:
SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/259395
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a technique with which the formation of a crack in a cutting location of a mold-formed section can be suppressed when a runner portion connecting adjacent mold-formed sections is cut and removed. This semiconductor manufacturing device comprises: a plurality of cavities (23a, 23b) into which a molding resin is filled so that a plurality of mold-formed sections are formed; and at least one runner (24a) through which the molding resin flows, the runner being connected to a gate (25a) of one cavity (23a) of the cavities (23a, 23b) to which one end of the runner is adjacent, and being connected to a gate (25b) of the other cavity (23b) of the cavities (23a, 23b) to which the other end of the runner is adjacent. The height position of an upper end on the one end side of the at least one runner (24a) is higher than the height position of an upper end on the other end side of the at least one runner (24a).
Inventors:
SAKAMOTO KEN (JP)
ICHIKAWA KEITARO (JP)
ICHIKAWA KEITARO (JP)
Application Number:
PCT/JP2021/021839
Publication Date:
December 15, 2022
Filing Date:
June 09, 2021
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L21/56
Domestic Patent References:
| WO2016072012A1 | 2016-05-12 |
Foreign References:
| JP2010109314A | 2010-05-13 | |||
| JPH08250530A | 1996-09-27 | |||
| JPH02246349A | 1990-10-02 | |||
| JPH0919939A | 1997-01-21 | |||
| JPH06275671A | 1994-09-30 |
Attorney, Agent or Firm:
YOSHITAKE Hidetoshi et al. (JP)
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