Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/135631
Kind Code:
A1
Abstract:
The present invention comprises: an N+ layer 21 which is connected to a source line SL, N+ layers 30a, 30b which are connected to a bit line BL1, and N+ layers 30c, 30d which are connected to a bit line BL2, the layers being positioned at either end of Si columns 23a to 23d which vertically stand on a substrate 1 and are connected to the N+ layer 21; gate insulating layers 27a to 27d which surround the Si columns 23a to 23d; first gate conductor layers 28a, 28b which surround the gate insulating layers 27a to 27d and are connected to plate lines PL1, PL2; and second gate conductor layers 29a, 29b which are connected to word lines WL1, WL2. When perspectively viewed in cross sections along X1-X1' and X2-X2', the cross-sections of the Si columns 23a, 23c and the cross-sections of the Si columns 23b, 23d partially overlap with each other, respectively.
Inventors:
SHIROTA RIICHIRO (TW)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/000490
Publication Date:
July 20, 2023
Filing Date:
January 11, 2022
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
SHIROTA RIICHIRO (TW)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SHIROTA RIICHIRO (TW)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
H01L21/336; H01L27/105; H01L29/788; H01L29/792
Domestic Patent References:
| WO2014184933A1 | 2014-11-20 |
Foreign References:
| US20200135863A1 | 2020-04-30 | |||
| US20200013791A1 | 2020-01-09 | |||
| JP2003188279A | 2003-07-04 | |||
| JP2008147514A | 2008-06-26 | |||
| JP2008124209A | 2008-05-29 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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