Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/018875
Kind Code:
A1
Abstract:
Provided is a layout structure of a mask ROM that uses a complementary FET (CFET). A ROM cell comprises: a three-dimensional transistor (M00) provided between a bit line (11) and a ground power source line (62); and a three-dimensional structure transistor (M11) provided between a bit line (12) and a ground power source line (61). Channel units of the M00 and the M01 overlap in a plan view. First data is stored according to whether a source of the M00 and the ground power source line (62) are connected or not. Second data is stored according to whether source of the M01 and the ground power source line (62) are connected or not. The bit lines (11, 12) are formed in an embedded wiring layer.
Inventors:
SAKAI YASUMITSU (JP)
Application Number:
PCT/JP2023/024405
Publication Date:
January 25, 2024
Filing Date:
June 30, 2023
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H10B20/00
Domestic Patent References:
| WO2020230665A1 | 2020-11-19 | |||
| WO2020230666A1 | 2020-11-19 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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