Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2024/057941
Kind Code:
A1
Abstract:
A semiconductor memory device (1) comprises: a first pull-down N-channel MOS transistor (21) having a drain connected to a word line (20), a source connected to a ground line, and a gate connected to a first node (91); a first series-connected N-channel MOS transistor (22) having a drain connected to a power supply line, and a source connected to the first node (91); and a second series-connected N-channel MOS transistor (23) having drain connected to the first node (91), and a source connected to the ground line. A signal that is an inverted logic of a signal input to the gate of the second series-connected N-channel MOS transistor (23) is inputted to the gate of the first series-connected N-channel MOS transistor (22).
Inventors:
MOTOTANI ATSUSHI
Application Number:
PCT/JP2023/031714
Publication Date:
March 21, 2024
Filing Date:
August 31, 2023
Export Citation:
Assignee:
NUVOTON TECH CORPORATION JAPAN (JP)
International Classes:
G11C11/418; G11C7/04; G11C8/08
Foreign References:
| JPS61242390A | 1986-10-28 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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