Title:
SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2024/093153
Kind Code:
A1
Abstract:
Provided in the present disclosure are a semiconductor package structure and a manufacturing method therefor. The semiconductor package structure comprises an interposer layer, a conductive through hole and a capacitor, the conductive through hole and the capacitor being arranged in the interposer layer and spaced apart from each other, and two opposite ends of the conductive through hole respectively extending to a first face and a second face of the interposer layer. At least part of a first electrode layer of the capacitor is electrically led out of the interposer layer via the first face by means of a first conductive structure, and at least part of a second electrode layer of the capacitor is electrically led out of the interposer layer via the second face by means of a second conductive structure. The present disclosure can simplify the structure of the capacitor, reduce the manufacturing difficulty, and increase the capacitance.
Inventors:
CHEN JUN (CN)
WANG CHUNYANG (CN)
WANG CHUNYANG (CN)
Application Number:
PCT/CN2023/088778
Publication Date:
May 10, 2024
Filing Date:
April 17, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/64; H01L27/146
Foreign References:
| CN112397485A | 2021-02-23 | |||
| CN111180414A | 2020-05-19 | |||
| CN113809079A | 2021-12-17 | |||
| CN114256200A | 2022-03-29 | |||
| US20120119373A1 | 2012-05-17 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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