SEMICONDUCTOR PACKAGING ASSEMBLY AND PREPARATION METHOD

WIPO Patent Application WO/2024/007407

A1

Disclosed in the embodiments of the present disclosure are a semiconductor packaging assembly and a preparation method. The semiconductor packaging assembly comprises: a substrate, which has a first surface; a first chip structure, which is located on the substrate and is electrically connected to the first surface of the substrate; an interposer, which has a first interconnection surface, the first interconnection surface being provided with a first interconnection region and a second interconnection region, first solder balls being formed in the first interconnection region, first pads being formed in the second interconnection region, and the interposer being electrically connected to the first surface of the substrate by means of the first pads; and a plastic packaging material, which seals the first chip structure, the interposer and the first surface of the substrate, wherein each first solder ball has a surface that is exposed to the plastic packaging material, and a preset height is formed between the exposed surface of the first solder ball and the first interconnection surface of the interposer.

SUN XIAOFEI (CN)

PCT/CN2022/110303

January 11, 2024

August 04, 2022

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CHANGXIN MEMORY TECH INC (CN)

H01L23/31; H01L21/50; H01L21/56; H01L23/535; H01L23/538; H01L25/065; H01L25/18

US20100320582A1	2010-12-23
CN106711094A	2017-05-24
US20170069607A1	2017-03-09
CN105161435A	2015-12-16

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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