SEMICONDUCTOR MODULE

FIELD OF THE INVENTION

The invention relates to semiconductor modules and a method for producing such modules. In particular, the invention relates to semiconductor modules with a semiconductor stack arrangement.

BACKGROUND OF THE INVENTION

In many industrial applications, silicon-based devices, such as e.g. power semiconductor modules, are utilized. Requirements and demands set to such modules in terms of a power density that may be processed by the modules as well as demands in terms of a compactness of the modules are increasing.

Conventional semiconductor modules may currently approach their power and loss density limits. Further power density improvements and respective cost savings may only be expected via an increase of an operational temperature limit of the power semiconductor module or via an increase of a heat flux from the power semiconductor devices within the module.

An operation at high-temperature may for example be achieved by using so-called wide bandgap (WBG) semiconductors that may be applied in particular for fast switching power semiconductor modules requiring a rather compact module design with minimized stray impedances.

WO 2012/165559 A1 describes a laminated semiconductor module with a mounting structure that suppresses temperature rises accompanying heat generation of semiconductor devices in the semiconductor module.

US 6,219,237 B1 shows an electronic assembly 100 with an interposer 110 between two chips 125, 130 (see US 6,219,237 B1 column 3, lines 1 to 20). The interposer 110 is fabricated from semiconductor wafers 1 12, 114, which comprises cooling channels 116 (see US 6,219,237 B1 column 3, lines 54 to 62). DESCRIPTION OF THE INVENTION

An improved heat flux may further be achieved e.g. by increasing heat transfer coefficients at interfaces of the power semiconductor devices within the module, e.g. by a direct cooling closer to a semiconductor chip of the module, and/or by increasing surfaces transferring heat, e.g. by double-side cooling and/or stacking semiconductor chips of the semiconductor module. In conclusion to both approaches, significant benefit in terms of increased power density of the semiconductor module may be enabled by leaving a traditional 2D circuit layout and heading for an ideal arrangement in the third dimension.

A first step towards compactness and stacking of power semiconductors may be achieved by a planarization of the semiconductor topside. For example, wirebonds may be replaced by sputtered and plated Cu conductors, a double-sided cooling may be reached with soldered or sintered emitter and collector contacts, and solder bumps for direct bonded copper attachment. All of these approaches may come along with significant stray inductance reduction.

In addition, the power-density of a semiconductor module may be increased by a 3D arrangement of semiconductor chips. For example, bonding technologies like nano-Ag sintering and transient liquid phase bonding may be used to enable automated multi-layer bonding in one or multiple steps with final joints having superior thermal, mechanical and electrical properties, which may be regarded essential for a 3D assembly implementation and a reliability of the semiconductor module.

Examples for advanced chip cooling are: so-called microchannel single phase flow which may remove high heat fluxes but may require considerable pumping power for a cooling liquid; porous media flow which may provide a large surface area for heat transfer but may result in a very large pressure drop and a poor flow distribution; jet impingement cooling, which may reach low thermal resistances without any thermal interface material but may require multiple jets to yield to a uniform surface temperature and may tend to require a large pumping power; and microchannel two-phase flow boiling, which may consume low pumping power, may have a good temperature uniformity and may provide a high heat flux dissipation over 350 W/cm ² , but may involve rather high complexity.

For medium to high voltage power semiconductor modules, which may for instance be operated at voltages above approximately 100 V, however, certain challenges may need to be addressed and overcome to allow an increase in power density and a compact 3D assembly. For instance, insulation requirements may set minimum distances to avoid bulk insulation, internal surface and flashover breakdown. Operation of a power semiconductor chip at high-temperatures above 200 °C may require new insulator materials. Furthermore, thermal management of hard to access power loss sources within a 3D arrangement of semiconductor chips may be required. Apart from that, electromagnetic interference (EMI) and/or electromagnetic compatibility (EMC) issues related to very strong current and voltage transients at power semiconductor hard switching may need to be addressed. Moreover, issues related to reliability and robustness, which may occur due to a mismatch in coefficient of thermal expansion (CTE) leading to thermo-mechanical stress and fatigue degradation, due to higher field stresses for WBG devices, and due to stressors by novel environmental factors, such as e.g. outdoor, offshore, subsea or on- vehicle operation, may need to be addressed. Also issues related to manufacturability may impose strong requirements on process precision, process integration and compatibility for multiple joining processes as well as respective process yields and costs.

The need for a 3D design, however, may become particularly relevant for high-voltage devices where capacitive coupling to a baseplate and/or to a heat sink may lead to considerable leakage currents. For example, a SiC module operated at 10 kV and 200 A based on 40 semiconductor chips, such as e.g. 10 A rated MOSFETs and/or diodes, with a turn-on/off time of 50 ns may generate a leakage current through the baseplate of 22 A, which may be induced by coupling through 2 mm thick, 50 cm ² substrate with a drain Cu area of 25 cm ² .

It is an objective of the present invention to overcome at least some of the above mentioned problems. It is a further objective of the present invention to provide a compact design of a semiconductor module with enhanced power and thermal characteristics.

These objectives are achieved by the subject-matter of the independent claims. Further exemplary embodiments are evident from the dependent claims and the following description.

A first aspect of the invention relates to a semiconductor stack arrangement. The semiconductor stack arrangement comprises a first semiconductor chip with a planar terminal mounted to a side of the first semiconductor chip; a second semiconductor chip with a planar terminal mounted to a side of the second semiconductor chip (which may be opposite to the side of the first semiconductor chip); and an interposer arranged between the first semiconductor chip and the second semiconductor chip for electrically connecting the planar terminal of the first semiconductor chip and the planar terminal of the second semiconductor chip. Therein a first side of the interposer is in thermal contact with the planar terminal of the first semiconductor chip and a second side of the interposer is in thermal contact with the planar terminal of the second semiconductor chip. The interposer comprises at least one channel or a plurality of channels adapted for cooling the first semiconductor chip and the second semiconductor chip. Accordingly the interposer may be adapted for cooling the semiconductor stack arrangement.

The term "semiconductor stack arrangement" may refer to an arrangement of at least two semiconductor chips, such as e.g. carrying a diode, a MOSFET, an IGBT, a BIGT, and/or other semiconductor devices, which may be arranged and/or stacked on top of each other (i.e. orthogonal to an extension of a mounting plate carrying the stack), thereby providing a compact layout in three dimensions. The semiconductor stack arrangement may comprise multiple semiconductor chips of a same kind/type or of different kinds/types (that may be arranged along an extension of a mounting plate carrying the stacks).

The term "planar terminal" may refer to a flat electrical connection of a semiconductor chip, which may be arranged e.g. on a top and/or a bottom side of the chip and which may be adapted for electrically connecting various devices and/or parts of the semiconductor chip. The "planar terminal" may, thus, refer to a bare side of the semiconductor chip and/or a side which may be contacted by some further contacting element, such as e.g. a plate of electrically conducting material (e.g. Cu and/or Ag).

The term "interposer" may refer to a separating element, which may spatially separate the semiconductor chips while providing an electrical connection between the planar terminals of the respective semiconductor chips.

Apart from that, the interposer may provide a thermal connection between the semiconductor chips and the interposer, such that thermal energy generated by the semiconductor chips may be transferred from the semiconductor chips via the respective planar terminals to the interposer, e.g. by thermal conduction, convection and/or radiance. Therefore, the term "thermal contact" may refer to a thermal connection between a thermally emitting surface and/or the planar terminal of the respective semiconductor chip and a surface of the interposer, such that heat may be conducted to the interposer.

The at least one channel of the interposer may extend substantially parallel, substantially orthogonal or along an inclined direction with respect to the planar terminal, and it may for instance have a rectangular, a quadratic or a circular cross-section with a diameter of at least 5%, preferably between 10% and 50%, of a thickness of the interposer. The plurality of channels of the interposer may for instance comprise at least three channels, preferably e.g. between 5 and 20 channels, which may be arranged in a single row or multiple rows in the interposer. Each of the channels may have a rectangular, a quadratic or a circular cross-section with a diameter of e.g. at least 1 % of a thickness of the interposer, preferably between e.g. 3% and 15%o. The channels may extend along a direction substantially parallel and/or substantially orthogonal to the planar terminals. However, the channels may also extend along an inclined direction with respect to the planar terminals. Apart from that, the channels may be directed substantially parallel with respect to each other or the plurality of channels may be directed in various directions, i.e. they may be directed and/or arranged in an arbitrary pattern in the interposer.

By arranging and/or stacking the semiconductor chips in three dimensions in a semiconductor stack arrangement with an interposer structure as described above, a design and/or layout of the semiconductor stack arrangement and consequently a design and/or layout of a semiconductor module comprising such stack arrangement, such as e.g. a half-bridge arrangement and/or half-bridge semiconductor module, may be provided in a compact manner.

According to an embodiment of the invention, the planar terminal of the first semiconductor chip is an inner planar terminal and the first semiconductor chip comprises an outer planar terminal on an opposite side of the first semiconductor chip; and/or the planar terminal of the second semiconductor chip is an inner planar terminal and the second semiconductor chip comprises an outer planar terminal on an opposite side of the second semiconductor chip.

The term "inner planar terminal" may refer to a planar terminal arranged within a stacked structure of the stack arrangement, i.e. a terminal arranged in an inner part of the stack arrangement. On the other hand, the "outer planar terminal" may refer to a terminal arranged on an outside of the stack arrangement.

According to an embodiment of the invention the stack arrangement comprises a second interposer electrically and thermally connected to an outer planar terminal of the first or second semiconductor chip. Additionally or alternatively, the stack arrangement may comprise a short-circuit failure block between the interposer and one of the first and the second semiconductor chip adapted for forming an eutectic alloy with a material of the semiconductor chip.

By arranging a further interposer on a further side of a semiconductor chip, an efficiency of cooling and/or heat transfer from the semiconductor chip to the interposers may be enhanced since the respective semiconductor chip may be cooled from at least two sides.

Additionally by arranging and/or stacking interposers and semiconductor chips in an alternating manner on top of each other, a stack arrangement comprising basically any number of semiconductor chips may be provided in a compact layout, i.e. the stack arrangement may be scalable to basically an arbitrary extent. The short-circuit failure block may advantageously increase a safety of the stack arrangement. The short-circuit failure block may for instance comprise a block of e.g. Al and/or Ag which may melt in case of a failure of a semiconductor chip and/or the entire stack arrangement, such as e.g. a short-circuit. Molten material of the short-circuit failure block may penetrate at least a part of a semiconductor chip, thereby forming an eutectic alloy with Si material of the chip. This may provide a low-resistive electrical contact, which in turn may allow large amounts of current to flow through that contact. In this way the module can further support current flow, which is relevant for power electronic topologies with series connected power modules. In addition, a violent end-of-life with arcing of modules may be prevented.

According to an embodiment of the invention, the interposer comprises a layer structure with a first layer, a second layer and a central layer arranged between the first layer and the second layer, which is made of a different electrically conducting material as the first and second layer. Therein the at least one channel or the plurality of channels of the interposer are arranged in the central element. The first and second layer may be suited for being bonded with the semiconductor chips and/or may have the same or nearly the same thermal expansion coefficient as the semiconductor chips. The central layer may be made of a cheaper material and/or may be adapted for being machined for manufacturing the at least one channel or the plurality of channels.

The first layer may be arranged on a first side of the central layer and the second layer may be arranged on a second side of the central layer, which second side opposes the first side.

The first and the second layer may for instance comprise Mo material and the central layer may e.g. comprise Cu material. However, the interposer may be manufactured from any suitable electrically and thermally conductive material and/or alloy. For instance the interposer may be entirely manufactured from Cu or Mo or a MoCu alloy.

According to an embodiment of the invention, the interposer comprises an inner chamber extending between the first and/or second side of the interposer and the at least one channel or the plurality of channels, which chamber contains a cooling liquid and/or fluid for transferring thermal energy, i.e. heat, between the first and/or second side to the plurality of channels by performing a phase change. In other words, the inner chamber may be arranged within the interposer between a semiconductor chip, which may be in thermal contact with the first or second side of the interposer, and the at least one channel or the plurality of channels, which may be arranged in a central layer of the interposer. Cooling liquid/fluid present in the inner chamber may be evaporated in an evaporation region of the inner chamber, thereby absorbing thermal energy released from the semiconductor chip. The evaporation region may be arranged close to the side of the interposer facing the semiconductor chip. The evaporated cooling liquid/fluid, i.e. a steam or vapour of cooling liquid/fluid, may then condensate in a condenser region of the inner chamber, thereby releasing the absorbed thermal energy to the interposer and the at least one channel or the plurality of channels. The condenser region may for this purpose be arranged close to the at least one channel or the plurality of channels.

A further aspect of the invention relates to a power semiconductor module. The semiconductor module comprises at least one semiconductor stack arrangement as described in the above and in the following, and a mounting plate carrying the at least one semiconductor stack arrangement.

The term "power" semiconductor module may refer to voltages being processed by the semiconductor module above approximately 0.1 kV, for example above approximately 1 kV, and/or to currents in the order of several Ampere, for example above approximately 10 A.

The mounting plate may comprise a substrate plate, such as e.g. a direct bonded copper (DBC) substrate plate, which substrate plate may carry the stack arrangement on a first side. The at least one substrate plate may be mounted with a second side e.g. to a base plate, which second side may oppose the first side. The base plate may further be attached to a cooler and/or a heat sink on a side opposing the side of the base plate, on which the substrate plate may be attached.

Current layouts of semiconductor chips in semiconductor modules may essentially be two-dimensional. Such layouts may impose limits with respect to a power density and a capability to support hard switching e.g. of wide band gap (WBG) semiconductors.

By arranging and/or stacking the semiconductor chips in three dimensions in a semiconductor stack arrangement with an interposer structure as described above, a design of a semiconductor module, such as e.g. a half-bridge arrangement and/or a semiconductor module, may be provided in a compact manner. By this approach several benefits may be achieved simultaneously. For instance a footprint of the semiconductor module and thereby module costs may be reduced. Module costs may further be reduced by a design option without costly elements such as e.g. direct bonded copper (DBC) substrates, baseplates and/or large area coolers. Apart from that, an increase in power rating by direct cooling and optional double-side cooling, i.e. cooling on two sides of a semiconductor chip, may be achieved. Moreover, stray inductance may be minimized by short stack-to-stack commutation loops, and/or stray capacitance may be minimized by a small footprint, a vertical current flow and a low-permittivity insulation.

Moreover, a capability of modules employing WBG semiconductor chips operated at high temperatures may be provided because no wirebonds may be required, because all high temperature interfaces may be based on large-area joints with matched coefficients of thermal expansion (CTE), and because the interposer may act as strain buffer for terminal joints, such as e.g. Cu terminal joints.

Apart from that, an option to integrate a short-circuit failure mode capability to the semiconductor module may be provided as well.

Additionally, an option for a compact single-stack half-bridge arrangement may be provided by use of bi-mode, reverse blocking semiconductor devices. Furthermore, a flexibility may be enhanced by modular half-bridge units, which may have plastic enclosures, that may be easily paralleled. Such design may be in particular suitable for an application of WBG semiconductors in the semiconductor module.

According to an embodiment of the invention, the power semiconductor module further comprises at least one feeding duct adapted for providing a cooling liquid to the interposer; and at least one purging duct adapted for purging the cooling liquid from the interposer. Therein, the at least one feeding duct is connected to an inlet of the interposer, which inlet is connected to the at least one channel or to at least one of the plurality of channels, and the at least one purging duct is connected to an outlet of the interposer, which outlet is connected to the at least one channel or to at least one of the plurality of channels.

By providing cooling liquid via the feeding duct to the interposer, which cooling liquid may have a rather low temperature, it may be ensured that a rather large gradient in temperature from regions of the interposer close to the semiconductor chips to regions of the interposer close to the at least one channel or to the plurality of channels may be present. In other words, a rather large temperature difference between these respective regions may be present. This may ensure an efficient transfer of thermal energy from the semiconductor chips to the cooling liquid. Moreover by purging already heated cooling liquid from the interposer it may be ensured that only few or no heated cooling liquid may remain for a long period of time within the channel or the channels. This may further ensure that the temperature gradient and thus an efficient cooling of the semiconductor chips may be sustained.

The inlet and the outlet may for this purpose each comprise an attachment means and/or an attachment element, which may be adapted for detachably attaching and/or fixating the feeding duct and the purging duct on the interposer. The inlet and the outlet may further comprise a sealing element, such as e.g. a sealing lip, which may be adapted for providing a leackproof connection of the feeding duct and the purging duct with the inlet and the outlet, respectively. The inlet and the outlet may further comprise at least one valve, which may be adapted for controlling a flow of cooling liquid into and/or out of the interposer.

The feeding duct may be attached to a pump, which may be adapted for pumping cooling liquid into the feeding duct and via the inlet into the at least one channel or the plurality of channels of the interposer. The purging duct may be attached to a suction pump, which may be adapted for sucking cooling liquid from the at least one channel or the plurality of channels of the interposer via the outlet into the purging duct. Both feeding duct and purging duct may be part of a closed cooling circuit, which may further comprise the inlet, the outlet, at least one pump, a heat exchanging device, and the channel or the plurality of channels of the interposer themselves.

According to an embodiment of the invention, the at least one feeding duct and the at least one purging duct are made of a flexible and insulating material, such as e.g. Teflon and/or plastic material.

The cooling liquid may for instance comprise de-ionized water and/or any other dielectric fluid, such as e.g. Hydro-Fluoro-Ether.

According to an embodiment of the invention, the power semiconductor module further comprises at least one insulating spacing element mounted to the mounting plate and carrying the at least one semiconductor stack arrangement.

Such arrangement may allow a cavity to be present between the mounting plate and the semiconductor stack arrangement, which may advantageously reduce a stray capacitance of the module by realizing a low-permittivity and wide-distance separation between voltage loaded circuits to grounded baseplates and coolers. Apart from that, there might be no need for a costly baseplate and/or substrate plate, on which the semiconductor stack arrangement may be mounted. Consequently, production costs and/or semiconductor module costs may be reduced.

According to an embodiment of the invention, the power semiconductor module comprises at least two semiconductor stack arrangements arranged in juxtaposition with each other, each having an interposer.

This may allow combining various semiconductor stack arrangements of a same kind/type or of different kinds/types within one semiconductor module. For example two stack arrangements with a symmetric or an anti-symmetric arrangement of e.g. a semiconductor switch and a diode may be combined. In general this may provide a flexibility with respect to a layout and/or design of the module as well as a certain flexibility in terms of electrical connections within the module. Consequently this flexibility may further allow manufacturing a compact module, such as e.g. a compact half-bridge configuration. Such half-bridge configuration or half bridge arrangement may for instance comprise four semiconductor chips arranged in a first and a second semiconductor stack arrangement, respectively, wherein each stack arrangement may comprise a semiconductor switch and a diode with an interposer arranged in between. An electrical input and/or a planar terminal of the diode of the first stack arrangement may for example be electrically connected to an electrical output and/or a further planar terminal of the diode of the second stack arrangement.

According to an embodiment of the invention the interposers of at least two stack arrangements are integrally formed. In other words, the at least two stack arrangements may have common interposers. The interposers may be formed in one piece and/or they may be mechanically interconnected, e.g. by a bridge element.

According to an embodiment of the invention, a first interposer of a first stack arrangement and a second interposer of a second stack arrangement are interconnected with a duct such that a cooling liquid is conducted between the at least one channel or the plurality of channels of the first interposer and the at least one channel or the plurality of channels of the second interposer.

This may allow interconnecting various stack arrangements within the module in a closed circuit of cooling liquid, wherein the cooling liquid may flow via the duct from one interposer of one stack arrangement to a further interposer of a further stack arrangement, thereby cooling each stack arrangement. Apart from that, only one feeding duct and one purging duct may be required for the entire semiconductor module since cooling liquid may be provided via the feeding duct to one stack arrangement and then conducted via the duct to the further stack arrangement. Similarly, cooling liquid from the entire semiconductor module may be purged from various stack arrangements via a single purging duct. Consequently, such arrangement may reduce parts, which may be required for a comprehensive and efficient cooling of the various stack arrangements, and it may reduce costs of the semiconductor module. However, the semiconductor module may comprise multiple inlets and/or outlets, which may be connected to multiple feeding ducts and/or purging ducts, respectively.

A further aspect of the invention relates to a use of an electrically conducting interposer comprising at least one channel or a plurality of channels for cooling a semiconductor stack arrangement. The interposer is arranged between a planar terminal of a first semiconductor chip of the stack arrangement and an opposite planar terminal of a second semiconductor chip of the stack arrangement.

Another aspect of the invention relates to a method of manufacturing a semiconductor stack arrangement. The method comprises the steps of: providing an interposer, which comprises at least one channel or a plurality of channels; providing a first semiconductor chip with a first planar terminal and a second semiconductor chip with a second planar terminal; arranging the interposer between the first semiconductor chip and the second semiconductor chip, such that the first planar terminal is in contact with a first side of the interposer and the second planar terminal is in contact with a second side of the interposer; and simultaneously bonding the first terminal to the first side and the second terminal to the second side.

According to an embodiment of the invention, bonding of the interposer comprises soldering, sintering and/or transient liquid phase bonding and/or the at least one channel or the plurality of channels are machined into the interposer, such as e.g. by drilling.

Generally the method described above may further comprise metalizing at least a part of a side of the first and a side of the second semiconductor chips, at least a part of the first and the second planar terminals, and/or at least a part of a side of the interposer.

Moreover, the method of manufacturing a semiconductor stack arrangement may further comprise mechanically fixing the stack arrangement. This may comprise aligning joining partners, such as e.g. semiconductor chips and interposer, including e.g. bond layers between the joining partners by a position fixture equipment and/or by a pick and place equipment.

Apart from that, the method of manufacturing a semiconductor stack arrangement may further comprise heating the stack arrangement under a temperature profile.

It has to be understood that features of the method as described in the above and in the following may be features of the stack arrangement and/or the semiconductor module as described in the above and in the following.

If technically possible but not explicitly mentioned, also combinations of embodiments of the invention described in the above and in the following may be embodiments of the method and the stack arrangement and/or the semiconductor module.

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings.

Fig. 1 schematically shows a semiconductor stack arrangement according to an embodiment of the invention.

Fig. 2 schematically shows a semiconductor stack arrangement according to another embodiment of the invention.

Fig. 3A schematically shows an interposer with a semiconductor chip for a semiconductor stack according to an embodiment of the invention.

Fig. 3B schematically shows a cross-section through the interposer of Fig. 3A.

Fig. 3C schematically shows a cross-section through an interposer for a semiconductor stack according to an embodiment of the invention.

Fig. 3D schematically shows a cross-section through an interposer for a semiconductor stack according to a further embodiment of the invention.

Fig. 4 schematically shows a power semiconductor module according to an embodiment of the invention.

Fig. 5 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 6 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 7 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 8A schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 8B schematically shows a perspective view of the power semiconductor module of Fig. 8A.

Fig. 9 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 10 schematically shows a top view of a power semiconductor module according to a further embodiment of the invention.

Fig. 1 1 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 12 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 13 schematically shows a power semiconductor module according to a further embodiment of the invention. Fig. 14 schematically shows a power semiconductor module according to a further embodiment of the invention.

Fig. 15 shows a flow chart illustrating a method for manufacturing a semiconductor stack arrangement according to an embodiment of the invention.

The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Fig. 1 schematically shows a semiconductor stack arrangement 100 with a first semiconductor chip 102 and a second semiconductor chip 104, which may carry devices like IGBTs, BIGTs MOSFETs, freewheeling diodes and/or any other semiconductor devices.

The first semiconductor chip 102 comprises a planar terminal 106 mounted to a side 108 of the semiconductor chip 102. The planar terminal 106 is an inner terminal with respect to the stack arrangement 100. The planar terminal 106 may for instance be a region of the semiconductor chip 102, which may be electrically contacted. A part of the semiconductor chip besides the planar terminal 106 of Fig. 1 is contacted with a wire bond 107, which may be provided for gate control of the first semiconductor chip 102. The wire bond 107 is further contacted with a gate terminal 109. The first semiconductor chip 102 further comprises a further planar terminal 1 10 mounted to a further side 1 12 of the first semiconductor chip 102, which further side 1 12 opposes the side 108. The further planar terminal 1 10 is an outer terminal with respect to the stack arrangement 100 and it is in electrical contact with an electrically conductive element 114, which may for instance be an electrically conductive plate, layer or foil. The conductive element 1 14 may be bonded to the planar terminal 110 e.g. by Ag sintering, transient liquid phase bonding and/or soldering.

The second semiconductor chip 104 comprises a planar terminal 116 mounted to a side 1 18 of the semiconductor chip 104. The planar terminal 1 16 is an inner terminal with respect to the stack arrangement and is in electrical contact with an electrically conductive element 120, which may for instance be an electrically conductive plate, layer or foil. The second semiconductor chip 104 further comprises a further planar terminal 122 mounted to a further side 124 of the second semiconductor chip 104, which further side 124 opposes the side 1 18. The further planar terminal 122 is an outer terminal with respect to the stack arrangement 100 and is in electrical contact with an electrically conductive element 126, which may for instance be an electrically conductive plate, layer or foil. The conductive elements 120, 126 may be bonded to the planar terminal 116, 122 e.g. by Ag sintering, transient liquid phase bonding and/or soldering.

The first semiconductor chip 102 and the second semiconductor chip 104 each may comprise a junction edge termination area close to a border of the side 108 and the side 124, respectively, which sides 108 and 124 may refer to top-sides of the respective semiconductor chips 102, 104. These areas may not be entirely bonded with the planar terminal 106 or the planar terminal 122, respectively, because a minimum insulation distance d between the planar terminals 106 and the interposer 128 as well as between the planar terminal 122 and the conductive element 126 may be required, as illustrated by arrows in Fig.1. The bottom-side of each semiconductor chip 102, 104, i.e. the sides 112 and 118, may be fully planar and no edge termination area may be present. The edge termination area on the sides 108 and 124 of the semiconductor chips 102 and 104, respectively, may not be covered with the conductive element 126 or the interposer 128, respectively. The minimum insulation distance d may for instance be given by U _max /d < 20 kV/mm, e.g. by U _ma x/d < 10 kV/mm, and preferably by U _m ax/d < 5 kV/mm, wherein Umax may denote a blocking voltage of the semiconductor stack arrangement 100 and/or a blocking voltage of a semiconductor module comprising the stack arrangement 100.

The semiconductor stack arrangement 100 further comprises an interposer 128, which is arranged between the first semiconductor chip 102 and the second semiconductor chip 104. The interposer 128 comprises a first side 130, which is in thermal contact with the planar terminal 106 of the first semiconductor chip 102, and a second side 132, which is in thermal contact with the planar terminal 116 of the second semiconductor chip 104. Accordingly, the interposer 128 electrically connects the planar terminals 106, 116 of the first and the second semiconductor chips 102, 104. The interposer 128 further comprises a plurality of channels 134, which are adapted for cooling the first and the second semiconductor chips 102, 104. The channels 134 may for instance be microchanneis. The interposer 128 may be manufactured from a CTE matched material, such as e.g. Mo, a Cu/Mo composite or Silicon.

The interposer may act as a heat spreader only or it may be actively cooled by the integrated plurality channels 134 by providing a cooling liquid to the plurality of channels 134, as described in more detail hereinafter.

Fig. 2 schematically shows a semiconductor stack arrangement 100 with a first semiconductor chip 102 and a second semiconductor chip 104. If not stated otherwise, the stack arrangement 100 of Fig. 2 may comprise the same features and elements as the stack arrangement of Fig. 1. The stack arrangement comprises an interposer 128', which is arranged between the first semiconductor chip 102 and the second semiconductor chip 104. The first side 130 of the interposer 128' is bonded with a bonding layer 135 to the planar terminal 106 of the first semiconductor chip 102, and the second side 132 of the interposer 128'is bonded with a bonding layer 135'to the planar terminal 1 16 of the second semiconductor chip 104.

The interposer 128' resembles an approach to increase a heat spreading angle and an overall heat transfer of heat generated by the first and the second semiconductor chips 102, 104, respectively. Decreasing the CTE of the interposer 128' to match that of the first and second semiconductor chips 102, 104, such as e.g. a Cu/Mo compound, may come at the expense of thermal conductivity which in turn may reduce heat spreading and may increase a hot spot development. This may be mitigated by the interposer 128' as illustrated in Fig. 2 and explained in the following.

The interposer 128' comprises a first inner chamber 136 extending between the first side 130 of the interposer 128' and a central region 138 of the interposer 128' comprising the plurality of channels 134. The interposer 128' further comprises a second inner chamber 136' extending between the second side 132 of the interposer 128' and the central region 138.

The inner chambers 136, 136' contain a cooling liquid for transferring heat, which is generated by the first and the second semiconductor chips 102, 104, from the first and the second side 130, 132 of the interposer 128' to the central region 138 and the plurality of channels 134 by performing a phase change. For this purpose the first inner chamber 36 comprises an evaporation region 140 arranged close to the first side 130 and close to the first semiconductor chip 102. The first inner chamber 136 further comprises a condenser region 142 arranged close to the central region 138 and the plurality of channels 134. The second inner chamber 136' comprises a respective evaporation region 140' and a respective condenser region 142'. Cooling liquid in the inner chambers 136, 136' may be evaporated in the evaporation regions 140, 140', thereby absorbing thermal energy released from the first and the second semiconductor chips 102, 104. Evaporated cooling liquid, i.e. steam or vapour of cooling liquid, may then condensate in the respective condenser regions 142, 142' of the first and second inner chamber 136, 136', thereby releasing the absorbed thermal energy to the central region 138 and the plurality of channels134.

Accordingly, the interposer 128' as described above may consist of both passive and active strata. The passive strata, i.e. the inner chambers 136, 136' may consist of a closed two-phase system comprising e.g. a porous wicking material and an evaporation region 140, 140' and a condenser region 142, 142' using capillary driven liquid and vapour transport, rather than e.g. conduction, to spread dissipated heat with minimal temperature drop. Such two-phase structure may exhibit a thermal resistance reduction of more than 40% compared to e.g. a solid Cu/Mo interposer structure. The active strata, i.e. the central region 138, comprises the plurality channels, such as e.g. a plurality of integrated microchannels, which may remove net heat from the stack arrangement 100 via forced convective cooling. The coolant used may be a dielectric fluid, such as e.g. de-ionized water, and/or a refrigerant. The interposer 128' may have several advantages. Amongst others, a heat spreading ability of the low CTE material of the interposer 128' may be enhanced. Moreover, the passively heat spreading inner chambers 136, 136' may operate independently of an orientation due to a capillary driven fluid flow along the evaporation regions 140, 140'. Furthermore, a local flux at the microchannel level may remain within a 300W/cm ² limit while a heat flux at the chip level may be higher, which may be the case e.g. for SiC semiconductor chips having a smaller footprint area and heat fluxes above 300W/cm ² . Additionally, a proximity of the adjacent semiconductor chips may be increased maintaining a low inductance without concern for thermal hot spots, and the passive and active strata may be fabricated e.g. using mature etching and machining processes.

Similar as the interposer 128 of Fig. 1 , the interposer 128 may have a wider extension as the chips 12, 104 in direction orthogonal to the stacking direction of the stack 100. This may increase the cooling capability of the interposer 128, 128'. Also the chambers 136, 136' may have such a wider extension, which may increase their heat transfer capability.

Fig. 3A schematically shows an interposer 128 with a semiconductor chip 104. The semiconductor chip 104 is arranged on the second side 132 of the interposer 128. If not stated otherwise, the interposer 128 of Fig. 3A comprises the same elements and features as the interposer 128 of Fig. 1 and/or also may contain one or both of the chambers 136, 136' of Fig. 2.

The interposer of Fig. 3A comprises a layer structure with a first layer 144, a second layer 146 and a central layer 148 arranged between the first layer 144 and the second layer 146. The central layer 148 is made of a different electrically conductive material than the first and the second layers 144, 146. For instance, the first and the second layers 144, 146 may comprise Mo as material, whereas the central layer may comprise Cu as material.

Such material solution for the interposer 128 with a Mo/Cu/Mo laminate may have certain advantages. For instance the central region comprising Cu may have superior thermal conductivity, low cost and well suitability for machining. The Cu central layer may be sandwiched between two rather thin Mo layers as shown in Fig 3A. The plurality of channels 134 is arranged in the central layer 148 of the interposer 128. The channels 134 may for example be drilled into the Cu, whereas high cost Mo material fraction may be minimized. The channels 134 may extend so deeply into the central layer 148 that a hydraulic diameter of the channels 134 may be small but a channel surface area may be large. Making the channels 134 too small may result in an unreasonable pressure drop. A suitable size of the channels 134 may be in the range of approximately 100 micron width by 1 mm height.

Fig. 3B, 3C and 3D schematically shows a cross-section along a plane through a plurality of channels 134 through an interposer 128. If not stated otherwise, the interposer 128 of Fig. 3B, 3C and 3D may comprise the same elements and features as the interposer 128, 128' of Figs. 1 , 2 and 3A.

With respect to Fig. 3B, the channels 134 penetrate entirely through the interposer 128 and are arranged parallel with respect to each other.

As can be seen in Fig. 3C, the plurality of channels 134 are arranged in a grid-like structure, wherein various channels 134a extend along a longitudinal direction of the interposer 128 and various other channels 134b extend along a vertical direction of the interposer 128, thereby crossing the channels 134a. Therein all channels 134 entirely penetrate the interposer 128. In general, at least two channels of the plurality of channels 134 may cross each other.

As can be seen in Fig. 3D, the plurality of channels 134 are arranged in a semi-circle like pattern within the interposer 128.

Fig. 4 schematically shows a power semiconductor module 400 with a semiconductor stack arrangement 100. If not stated otherwise, the stack arrangement 100 of the semiconductor module 400 of Fig. 4 may comprise the same elements and features as the stack arrangement 100 of Fig. 1.

The power semiconductor module 400 comprises a mounting plate 402 carrying the semiconductor stack arrangement 100. The mounting plate 402 comprises a baseplate 404, on which a substrate plate 406 is mounted. The substrate plate 406 may for instance be a direct bonded copper (DBC) substrate plate, which may be made of an insulating ceramics material.

On a side of the substrate plate 406 opposing the baseplate 404, a planar terminal 110 of a first semiconductor chip 102 is electrically connected to a terminal contact element 412. A planar terminal 1 16 of a second semiconductor chip 104 is electrically connected via a conductive element 120 to a further terminal contact element 408. The conductive element 120, which may be strip of conductive material, thus may be arranged between the interposer 128 and the second chip 104. Furthermore, a planar terminal 122 is electrically connected via a conductive element 126 to a terminal contact element 410. The terminal contact elements 408, 410, 412 may e.g. be islands of Cu material arranged on the substrate plate 406, wherein an insulation of the terminals may be ensured by separation of the various terminal contact elements 408, 410, 4 2 on the substrate plate 406.

Apart from that, a gate terminal 109, which is connected to the first semiconductor chip 102 by a wire bond 107 is also arranged on the substrate plate 406 and separated from the terminal contact elements 408, 410, 412.

For example one of the chips 102, 104 may comprise a controllable semiconductor switch, while the other one of the chip 102, 104 may comprise a diode, which may be a freewheeling diode for the switch.

The power semiconductor module 400 may further comprise an encapsulation to the semiconductor stack arrangement, that may be based on a polymeric insulator such as e.g. a Silicone gel, a Silicone rubber, Epoxy or Polyurethane in order to insulate the module 400.

Fig. 5 schematically shows a power semiconductor module 400 with a semiconductor stack arrangement 100. If not stated otherwise, the power semiconductor module 400 of Fig. 5 may comprise the same features and elements as the power semiconductor module 400 of Fig. 4.

The power semiconductor module 400 of Fig. 5 further comprises spacing elements 414 and 414' mounted to the mounting plate 402 and carrying the semiconductor stack arrangement 100, such that the stack arrangement 100 is spaced from the mounting plate 402. The spacing elements 414, 414' may for instance be pen-like elements or a framelike element, such as e.g. an insulated fixture frame. As a consequence of the spacing elements 414, 414', a cavity 416 may be formed between the semiconductor stack arrangement 100 and the mounting plate 402.

The power semiconductor module 400 comprises planar terminals 106, 1 10, 1 16, 122, which may be directly used as module terminals. Furthermore, a silicone gel encapsulation may provide an overall insulation of the power semiconductor module 400.

Fig. 6 schematically shows a power semiconductor module 400 with two semiconductor stack arrangements 100, 100' arranged in juxtaposition, i.e. arranged next to each other, on a mounting plate 402 comprising a baseplate 404 and a substrate plate 406. If not stated otherwise, the power semiconductor module 400 of Fig. 6 may comprise the same elements and features as the power semiconductor module 400 of Figs. 4 and/or 5. The stack arrangement 100 comprises a planar terminal 1 10 and the stack arrangement 100' comprises a planar terminal 1 10', which planar terminals 1 10, 1 10' are both connected to a terminal contact element 412. The terminal contact element 412 may in turn be connected to a further terminal contact element 408, i.e. the terminal contact elements 412 and 408 may have the same potential. The terminal contact element 408 is further connected to an electrical connection 418.

Moreover, the stack arrangement 100 comprises a planar terminal 122 and the stack arrangement 100' comprises a planar terminal 122', which are both connected via a conductive element 126 to a terminal contact element 410. The terminal contact element 410 is further connected to an electrical connection 418'.

The power semiconductor module further 400 further comprises a gate terminal 109 and a gate terminal 109' electrically connecting a semiconductor chip 102 of the stack arrangement 100 and a semiconductor chip 104' of the stack arrangement 100'.

As can be seen in Fig 6, the stack arrangements 100 comprise an interposer 128 and the stack arrangement 100' comprises an interposer 128', which interposers 128 and 128'are integrally formed. The interposers 128 and 128' may be formed in one piece or they may be mechanically interconnected by a bridge element 420. The interposers 128, 128' are further connected to an electrical connection 418".

The power semiconductor module 400 shown in Fig. 6 may for instance be a half- bridge module with asymmetric stack arrangements 100, 100' and the integrally formed interposers 128, 128' may be on a same potential, i.e. may be used for electrically interconnecting the two stack arrangements 100, 100'.

The term "asymmetric stack arrangements" may refer to the stack arrangement 100 having a first semiconductor chip 102 of a first kind, such as e.g. a switch, a diode, a MOSFET, or an IGBT, which first semiconductor chip 102 is arranged close to the substrate plate 406, whereas the stack arrangement 100' has a second semiconductor 104' of that first kind/type, which is arranged on an opposite side of the interposer 128'. Vice versa, the second semiconductor chip 104 of stack arrangement 100 and the first semiconductor chip 102' of stack arrangement 100' may be of a second kind/type.

The power semiconductor module 400 shown in Fig. 6 may provide very low stray inductance since stack to stack commutation loops may be spatially very close together. Moreover, the module 400 may provide very low stray capacitance due to a minimized footprint and a vertical rather than a horizontal current flow.

Initial stray impedance simulations have shown that a configuration of the semiconductor module 400 may lower the stray inductance by about one order of magnitude and the stray capacitance by about 50% as compared to a standard 2D arrangement within a conventional semiconductor module.

Fig. 7 schematically shows a power semiconductor module 400 with two semiconductor stack arrangements 100, 100' arranged in juxtaposition, i.e. arranged next to each other, on a mounting plate 402 comprising a baseplate 404 and a substrate plate 406. If not stated otherwise, the power semiconductor module 400 of Fig. 7 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4, 5 and/or 6.

In contrast to the power semiconductor module 400 of Fig. 6, the power semiconductor module 400 of Fig. 7 comprises symmetric stack arrangements 100, 100'. The term "symmetric stack arrangements" may refer to the stack arrangement 100 having a first semiconductor chip 102 of a first kind/type, such as e.g. a switch, a diode, a MOSFET, or an IGBT, which first semiconductor chip 102 is arranged close to the substrate plate 406, and the stack arrangement 100' having a first semiconductor 104' of that first kind/type, which is also arranged close to the substrate plate 406. Vice versa, the second semiconductor chip 104 of stack arrangement 100 and the second semiconductor chip 102' of stack arrangement 100' may be of a second kind/type.

The stack arrangement 100 comprises a planar terminal 110 and a planar terminal 122, which are connected to a terminal contact element 412. Also a planar terminal 1 16' of stack arrangement 100' is connected to the terminal contact element 412. The stack arrangement 100' further comprises a planar terminal 110' and a planar terminal 122', which are connected to a terminal contact element 412'. The terminal contact element 412 is further connected to an electrical connection 418", whereas the terminal contact element 412' is connected to an electrical connection 418. Moreover, the planar terminal 1 16 of the second semiconductor chip 104 of stack arrangement 100 is connected to an electrical connection 418'.

The power semiconductor module 400 of Fig. 7 may for instance be a half-bridge module with symmetric stacks and interposers 128, 128' on different potentials.

As the semiconductor module 400 of Fig. 6, also the semiconductor module 400 of Fig. 7 may provide very low stray inductance since the stack to stack commutation loops are spatially very close together, and it may provide very low stray capacitance due to a minimized footprint and vertical rather than horizontal current flow.

Fig. 8A and 8B schematically show a power semiconductor module 400, wherein Fig 8A shows a frontal view and Fig. 8B shows a perspective view. If not stated otherwise, the power semiconductor module 400 of Figs. 8A and 8B may comprises the same elements and features as the power semiconductor modules 400 of Figs. 4, 5, 6 and/or 7. The power semiconductor module 400 comprises a semiconductor stack arrangement 100 with a plurality of first semiconductor chips 102, which are arranged on a side of an interposer 128 and a plurality of second semiconductor chips 104 arranged on an opposite side of the interposer 128, which may comprise the same elements and features as the interposers of Fig. 1 to 3D.

The power semiconductor module 400 further comprises electrical connections 418, 418', 418", to which the semiconductor chips 102, 104 and the interposer 128 are electrically connected.

The semiconductor stack arrangement 100 is mounted to a mounting plate 402 with a spacing element 414, such that it is spaced from the mounting plate 402.

The power semiconductor module 400 further comprises a housing 422, which is filled with a Silicon gel for insulation purposes.

The power semiconductor module 400 further comprises a feeding duct 424 adapted for providing a cooling liquid, such as e.g. de-ionized water or Hydro-Fluoro-Ether, to the interposer 128. The semiconductor module 400 further comprises a purging duct 426 adapted for purging the cooling liquid from the interposer 128. The feeding duct 424 and the purging duct 426 may e.g. be Teflon and/or plastic material ducts. The feeding duct 424 is connected to an inlet 428 of the interposer 128, which inlet 428 is connected to at least one of the plurality of channels 134. The purging duct 426 is connected to an outlet 430 of the interposer 128, which outlet 430 is connected to at least one of the plurality of channels 134.

The inlet 428 and the outlet 430 may each comprise an attachment means and/or an attachment element, which may be adapted for detachably attaching and/or fixating the feeding duct 424 and the purging duct 426 on the interposer 128. The inlet 428 and the outlet 430 may further comprise a sealing element, such as e.g. a sealing lip, which may be adapted for providing a leackproof connection of the feeding duct 424 and the purging duct 426 with the inlet 428 and the outlet 430, respectively.

Also a Silicone gel, or more general an electrical insulation material, surrounding the semiconductor chips 102, 104 and the interposer 128 inside the housing 422 of the module 400 may provide for a sealing of the ducts 424 and 426 and/or their connection to the interposer 128.

The feeding duct 424 may be attached to a pump, which may be adapted for pumping cooling liquid into the feeding duct 424 and via the inlet 428 into the channels 134 of the interposer 128. The purging duct 426 may be attached to a suction pump, which may be adapted for sucking cooling liquid from the channels 134 of the interposer 128 via the outlet 430 into the purging duct 426.

The power semiconductor module 400, which comprises an insulating mounting plate 402 without e.g. a DBC substrate plate 406 may further reduce a stray capacitance. The stray capacitance reduction may be achieved by removing a ceramic substrate plate 406, which may have a high permittivity (er ~9-10), and using an insulating mounting plate 402 with low permittivity (er -3-4). The stray capacitance may further be reduced by increasing the distance between the stack arrangement 100 and the mounting plate 402, e.g. from approximately 2 mm to approximately 9 mm. Compared to a power semiconductor module 400 mounted to a DBC substrate plate 406, the stray capacitance to the mounting plate 402 may be reduced from about 130 pF to about 12 pF.

To allow for a superior power density in the power semiconductor module 400, the overall cooling provided to the semiconductor chips 102, 104 may have a value of thermal heat dissipation above about 200W/cm ² . Significant heat spreading may be available with the large interposer 128 of Fig. 8, but rather low spreading must be expected for the small interposer as for instance shown in Fig. 7. In order to be able to dissipate the anticipated high heat densities without significant heat spreading, two options are available: pumped liquid cooling or pumped two-phase cooling. A level of 300 W/cm ² cooling density may be reached using both options. De-ionized water may be the preferred fluid because of its superior thermal properties. Dielectric fluids such as HFE (HydroFluoroEther) refrigerants may be used as well e.g. for pumped two-phase cooling.

Fig. 9 schematically shows a power semiconductor module 400 with two semiconductor stack arrangements 100, 100' arranged in juxtaposition on a mounting plate 402 comprising a baseplate 404 and a substrate plate 406. If not stated otherwise, the power semiconductor module 400 of Fig. 9 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4, 5, 6, 7, 8A and 8B.

The semiconductor stack arrangements 100 each comprise an interposer 128', respectively, which interposers 128' each comprise a first inner chamber 136 and a second inner chamber 136', respectively. The interposers 128' may comprise the same features and elements as the interposer 128' of Fig. 2. Accordingly, the inner chambers 136, 136' contain a cooling liquid for transferring heat to the plurality of channels 134 by performing a phase change as described in more detail in Fig.2.

Fig. 10 schematically shows a top view of a power semiconductor module 400 comprising four semiconductor stack arrangements 100a-100d arranged in juxtaposition in a housing 422. The housing may be filled with an electrical insulation material, e.g. with Silicone gel or rubber material. If not stated otherwise, the power semiconductor module 400 of Fig. 10 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4 to 9.

Each of the stack arrangements 100a-100d comprise individual interposer 128a-128d, respectively.

The power semiconductor module 400 comprises two inlets 428 and 428', which may be connected to feeding ducts providing cooling liquid to the semiconductor module 400. The power semiconductor module 400 further comprises an outlet 430 which may be connected to a purging duct for purging cooling liquid from the semiconductor module 400. However, the semiconductor module 400 may have multiple inlets 428, 428' and outlets 430 arranged on the housing 422, which may be electrically insulated e.g. by Teflon tubes.

Cooling liquid provided to the semiconductor module 400 is distributed between the individual interposers 128a-128d and the corresponding channels within the interposers 128a-128d by a duct 432, which may comprise a grid-like structure interconnecting the interposers 128a-128d in series and/or in parallel with respect to each other. The duct 432 may be an insulating tube, e.g. a Teflon tube. A very high level of tightness may not be required since the surrounding Silicone gel and/or rubber may seal all interconnections. Apart from that, the interposers 128a-128d may have multiple ports for an optimized distribution of the cooling liquid. For example, the channels inside the interposers 128a- 128d may have crossings and/or junctions.

Fig. 1 1 schematically shows a power semiconductor module 400 with a stack arrangement 100. If not stated otherwise, the power semiconductor module 400 of Fig. 1 1 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4 to 10.

The semiconductor stack arrangement 100 comprises a first semiconductor chip 102 and a second semiconductor chip 104. A first interposer 128a is arranged between the first semiconductor chip 128a and the second semiconductor chip 128b. Additionally, a second interposer 128b is arranged on top of the semiconductor chip 104. As a consequence, a cooling performance provided by the first and second interposers 128a, 128b may be enhanced, in particular for the second semiconductor chip 104 since it is cooled from two sides, i.e. a full double-side cooling of the second semiconductor chip 104 is provided.

Fig. 12 schematically shows a power semiconductor module 400 with a stack arrangement 100. If not stated otherwise, the power semiconductor module 400 of Fig. 12 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4 to 1 1.

The semiconductor stack arrangement 100 comprises a first interposer 128a arranged on the mounting plate 402, a first semiconductor chip 102 arranged on top of the first interposer 128a, a second interposer 128b arranged on top of the first semiconductor chip 102, a second semiconductor chip 104 arranged on top of the second interposer 128b, and a third interposer 128c arranged on top of the second semiconductor chip 104. As a consequence, a cooling performance provided by the first, second and the third interposers 128a, 128b, 128c may be enhanced and both the first and the second semiconductor chips 102, 104 may be cooled from two sides, i.e. a full double-side cooling of both the first and the second semiconductor chips 102, 104 is provided.

Fig. 13 schematically shows a power semiconductor module 400 with a stack arrangement 100. If not stated otherwise, the power semiconductor module 400 of Fig. 13 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4 to 12.

The semiconductor stack arrangement 100 comprises a first short-circuit failure block 434 arranged between an interposer 128 and a first semiconductor chip 102. The semiconductor stack arrangement 100 further comprises a second short-circuit failure block 434' arranged on top of a second semiconductor chip 104 between the second semiconductor chip 104 and a conductive element 126.

The short-circuit failure blocks 434 and 434' may comprise a suitable preform material such as e.g. Ag or Al. The short-circuit failure blocks 434 and 434' may melt in case of a failure of a semiconductor chip 102, 104 and/or the entire stack arrangement 100, such as e.g. a short-circuit. The molten material of the short-circuit failure blocks 434, 434' may penetrate into at least a part of the respective semiconductor chips 102, 104, thereby forming an eutectic alloy with Si material of the semiconductor chips 102, 104. This may provide a low-resistive electrical contact, which in turn may allow large amounts of current to flow through that contact. Accordingly, the short-circuit failure blocks 434, 434' may provide an electrical bypass connection in case of a failure.

To enhance a lifetime of a short-circuit failure functionality of the power semiconductor module 400 using the short-circuit failure blocks 434, 434', a pressure load 436 may be applied from a top of the stack arrangement 100, e.g., by a spring. This may allow to compensate for geometry changes due to a melting of the preform materials of the short- circuit failure blocks 434, 434'.

Fig. 14 schematically shows a power semiconductor module 400 with a stack arrangement 100. If not stated otherwise, the power semiconductor module 400 of Fig. 14 may comprise the same elements and features as the power semiconductor modules 400 of Figs. 4 to 13.

The semiconductor stack arrangement 100 comprises three semiconductor chips 102, 104, 105 and three interposers 128a, 128b, 128c stacked on top of each other.

This may allow to realize more complex topologies of the power semiconductor module 400.

In general it may be possible to scale the semiconductor stack arrangement 100 in vertical direction to basically an arbitrary extent by applying multiple semiconductor chips and interposers. By this approach it may also be possible to arrange a full two-level half- bridge configuration in one semiconductor stack arrangement and to reduce a foot print of the semiconductor module 400 to a minimum. A similar result may be achieved by applying bi-mode reverse blocking devices, such as e.g. an BIGT. Note that such a "topology-in-the-module" approach may have many advantages, in particular it may allow for very compact power-electronics-building-block (PEBB) design and may help to suppress EMC/EMI issues at PEBB level.

Fig. 15 shows a flow chart illustrating a method for manufacturing a semiconductor stack arrangement 100.

In a first step S1 an interposer 128 is provided, which comprises a plurality of channels.

In a second step S2 a first semiconductor chip 102 with a first planar terminal 106 and a second semiconductor chip 104 with a second planar terminal 1 16 is provided.

In a third step S3 the interposer 128 is arranged between the first semiconductor chip 102 and the second semiconductor chip 104, such that the first planar terminal 106 is in contact with a first side 130 of the interposer 128 and the second planar terminal 1 16 is in contact with a second side 132 of the interposer 128. Simultaneously the first planar terminal 106 is bonded to the first side 130 and the second planar terminal 1 16 is bonded to the second side 132 in step S3.

The bonding of the interposer 128 in step S3 may comprise soldering, sintering and/or transient liquid phase bonding and/or the plurality of channels may be machined into the interposer 128, such as e.g. drilled.

Generally, in steps S1 and/or S2 at least a part of a side 108 and a further side 1 12 of the first semiconductor chip 102 as well as a side 118 and a further side 124 of the second semiconductor chip 104 may be metalized. Furthermore, at least a part of the first and the second planar terminals 106 and 1 16, and/or at least a part of the first side 130 and the second side 132 of the interposer 128 may be metalized in steps S1 and/or S2. Concerning sintering as bonding technique, metalizing may be carried out as follows: for instance the semiconductor chips 102, 104 may have e.g. suitable Ag metallization at a bottom side, and a top side may need Ag, Au or Cu metallization to be applied e.g. by sputtering. Other parts of the stack arrangement 100 may require Ag, Au, Cu coating as well. A preferred manufacturing process may be galvanic plating and/or sputtering. Apart from that, a bond layer transfer may be required e.g. by applying an Ag layer to one of the joining partners by either stencil printing of paste or by lamination, e.g. with low-pressure and/or low temperature film transfer.

Concerning transient liquid phase bonding as bonding technique, metalizing may be carried out as follows: a potential material system may be e.g. Cu/Sn/Cu, but other systems like Ag/Sn/Ag may also be suitable. A thick Cu layer may be applied on the semiconductor chips 102, 104 and the interposer 128, preferably by sputtering. Apart from that, a bond layer transfer may be required e.g. by applying a Sn layer by galvanic plating or a Sn foil with a layer thickness of e.g. 20 urn.

Moreover, step S3 of the method of manufacturing a semiconductor stack arrangement 100 may further comprise mechanically fixing the stack arrangement 100. This may comprise precisely aligning joining partners, such as e.g. the semiconductor chips 102, 104 and the interposer 128, including respective bond layers by a position fixture equipment and/or by a pick and place equipment.

Concerning sintering as bonding technique, mechanically fixing may further comprise applying sufficient pressure for a densification by either isostatic pressure, e.g. in liquid, in gas or in rubber, or uniaxial pressure via a spring concept or similar. A homogeneous pressure distribution may be essential for a bond quality.

Concerning transient liquid phase bonding as bonding technique, mechanically fixing may further comprise applying a load to keep interfaces in diffusion contact.

Apart from that, step S3 of the method of manufacturing a semiconductor stack arrangement 100 may further comprise heating the stack arrangement 100 under a temperature profile.

Concerning sintering as bonding technique, heating may comprise applying a pressure before a top temperature may be reached. A sintering process may be completed in less than 1 minute.

Concerning transient liquid phase bonding as bonding technique, heating may comprise applying a temperature profile, which may be well optimized to avoid on the one hand too quick Sn consumption, potentially leading to voids in the bond layer, and on the other hand to avoid too slow Sn diffusion, potentially leading to residual Sn in the bond layer. A process time may be in the order of hours.

In the method described above, it may be preferred to join material interfaces, e.g. of semiconductor chips 102, 104, interposer 128, planar terminals 106, 116, and/or mounting plate 402 by e.g. a process of Ag sintering or transient liquid phase bonding because they may allow both, either fabrication of the full structure in one step, or fabrication of multiple subsequent process steps since a final bond may withstand a considerably higher temperature as a top temperature of the process might be. Different bonding technologies may also be combined if necessary, e.g. a bottom side of the semiconductor chips 102, 104 may be rather suitable for sintering, whereas a top side of the semiconductor chips 102, 104 may be rather suitable for TLP. Ag sintering and TLP may both be mechanically robust, electrically and thermally highly conductive and lead free. Note that standard soldering may also be used but may rather require a full multi-layer bonding process in one step.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or controller or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

LIST OF REFERENCE SYMBOLS

100, 100', 100a, 100b, 100c, 100d semiconductor stack arrangement 102, 104 semiconductor chip

106, 110, 110', 116, 122, 122' planar terminal

107 wire bond

108, 112, 118, 124 side of semiconductor chip

109, 109' gate terminal

114, 120, 126 conductive element

128, 128', 128a, 128b, 128c, 128d interposer

130, 132 side of interposer

134, 134a, 134b plurality of channels

135, 135' bonding layer

136, 136' inner chamber of interposer

138 central region of interposer

140, 140 evaporation region

142, 142' condenser region

144 first layer of interposer

146 second layer of interposer

148 central layer of interposer

400 power semiconductor module

402 mounting plate

404 baseplate

406 substrate plate

408 410, 412, 412' terminal contact element

414 414 spacing element

416 cavity

418, 418', 418 electrical connection

420 bridge element

422 housing

424 feeding duct 426 purging duct

428, 428' inlet

430 outlet

432 duct

434, 434' short-circuit failure block

436 pressure load