Title:
SEMICONDUCTOR STORAGE UNIT AND METHOD FOR CONTROLLING SEMICONDUCTOR STORAGE UNIT
Document Type and Number:
WIPO Patent Application WO/2017/122418
Kind Code:
A1
Abstract:
The present invention makes it possible to minimize data writing failures in a semiconductor storage unit having a transistor for each memory cell. In a first transistor, a gate is connected to a gate signal line and a source is connected to a first source signal line. In a second transistor, a gate is connected to a gate signal line and a source is connected to a second source signal line. A storage element is connected to the drains of the first and second transistors. When storing data in the storage element, a gate signal line potential control unit performs control so as to increase the potential of the gate signal line to a prescribed high potential higher than a prescribed reference potential. A source signal line potential control unit decreases either one of the potentials of the first and second source signal lines to be lower than the prescribed reference potential on the basis of the data. A voltage clamp unit clamps either one of the potentials at a given potential when either one of the potentials decreases to the given potential lower than the prescribed reference potential.
Inventors:
OCHIAI YASUHIRO (JP)
Application Number:
PCT/JP2016/083259
Publication Date:
July 20, 2017
Filing Date:
November 09, 2016
Export Citation:
Assignee:
SONY CORP (JP)
International Classes:
G11C11/417; G11C11/413
Foreign References:
| JP2009151847A | 2009-07-09 | |||
| JP2002237192A | 2002-08-23 | |||
| JP2002101644A | 2002-04-05 | |||
| JP2002026254A | 2002-01-25 | |||
| JP2010257554A | 2010-11-11 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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