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Patent Searching and Data


Title:
SEMICONDUCTOR STRUCTURE LAYOUT AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/193337
Kind Code:
A1
Abstract:
The present disclosure provides a semiconductor structure layout, comprising: an active area pattern; a first-type gate pattern overlapping with the active area pattern, and extending along a first direction; and a metal layer pattern extending along the first direction, and in contact with the active area pattern on both sides of the first-type gate pattern by means of a contact hole pattern. In the semiconductor structure layout provided by embodiments of the present disclosure, the extension direction of the first-type gate pattern is consistent with that of the metal layer pattern, and compared with a structure in which the extension direction of the first-type gate pattern is perpendicular to that of the metal layer pattern, as the width of the first-type gate pattern in a second direction increases, the existence of the first-type gate pattern does not affect the overlapping between the metal layer pattern and the active area pattern, such that the length of the contact hole pattern connecting the metal layer pattern and the corresponding active area pattern can be increased under the condition of ensuring that the size of the first-type gate pattern meets the requirement, the reliability of the semiconductor structure formed by using the semiconductor structure layout is improved, and the device performance is optimized.

Inventors:
LI MINGHAO (CN)
ZHANG FENGQIN (CN)
SHANG WEIBING (CN)
Application Number:
PCT/CN2022/098102
Publication Date:
October 12, 2023
Filing Date:
June 10, 2022
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/407
Foreign References:
CN1790721A2006-06-21
CN114255802A2022-03-29
CN113760173A2021-12-07
CN109727980A2019-05-07
US20040233753A12004-11-25
Attorney, Agent or Firm:
SHANGHAI WINSUN INTELLECTUAL PROPERTY AGENCY (CN)
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