Title:
SEMICONDUCTOR STRUCTURE AND LAYOUT STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/060339
Kind Code:
A1
Abstract:
The embodiments of the present disclosure disclose a semiconductor structure, a memory, and a layout structure. The semiconductor structure comprises: a high-speed circuit module comprising a clock signal, the frequency of the clock signal being greater than a first threshold value; a first conductive metal layer, the first conductive metal layer comprising a plurality of power supply wires extending in a first direction and arranged at intervals, and being electrically connected to the high-speed circuit module; a redistribution layer located on the first conductive metal layer, the redistribution layer comprising: a plurality of power supply bonding pads, and a conductive wire connected to the power supply bonding pads; wherein the power supply bonding pads are located on one side of the high-speed circuit module, and a projection area of the power supply bonding pads does not overlap with the high-speed circuit module; the conductive wire comprises a first wire area formed by repeated bending back and forth, the first wire area at least partially covering the high-speed circuit module, and the conductive wire being used for electrically connecting the power supply wires to the power supply bonding pads.
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Inventors:
XU JING (CN)
JI KANGLING (CN)
JI KANGLING (CN)
Application Number:
PCT/CN2022/125615
Publication Date:
March 28, 2024
Filing Date:
October 17, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/52
Foreign References:
| US20060220215A1 | 2006-10-05 | |||
| US20210287965A1 | 2021-09-16 | |||
| CN114121883A | 2022-03-01 | |||
| CN114121082A | 2022-03-01 | |||
| CN110858572A | 2020-03-03 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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