Title:
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/231167
Kind Code:
A1
Abstract:
Embodiments of the present disclosure relate to the technical field of semiconductors, provide a semiconductor structure and a manufacturing method for a memory, and are used for solving the technical problem of poor integration of semiconductor structures. The semiconductor structure comprises a plurality of rows of memory groups, each row of memory groups comprises a plurality of memories arranged at intervals in a row direction, and in any two adjacent rows of memory groups, the memories in one row of memory groups and the memories in the other row of memory groups are arranged in a staggered manner, so that the space between adjacent memories can be reasonably utilized, the number of memories in the unit area is increased, and integration of the semiconductor structure is improved. In addition, in the embodiments, two memory cell arrays are integrated together, and the two memory cell arrays share one bit line structure, so that the size of a memory can be reduced, and integration of the semiconductor structure can be improved.
Inventors:
JIANG YI (CN)
XIAO DEYUAN (CN)
SU XINGSONG (CN)
LIU YOUMING (CN)
XIAO DEYUAN (CN)
SU XINGSONG (CN)
LIU YOUMING (CN)
Application Number:
PCT/CN2022/108202
Publication Date:
December 07, 2023
Filing Date:
July 27, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L27/108
Foreign References:
| CN112563276A | 2021-03-26 | |||
| CN109273457A | 2019-01-25 | |||
| CN111710678A | 2020-09-25 | |||
| CN114220765A | 2022-03-22 | |||
| CN107093604A | 2017-08-25 | |||
| CN113540092A | 2021-10-22 | |||
| US20180315758A1 | 2018-11-01 | |||
| US10475804B1 | 2019-11-12 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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