SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR

WIPO Patent Application WO/2023/236265

A1

Disclosed in the embodiments of the present disclosure are a semiconductor structure and a manufacturing method therefor. The semiconductor structure comprises a substrate, first gate electrode structures, second gate electrode structures, and covering layers, wherein the substrate comprises discrete semiconductor channels, which are arranged on the top of the substrate and extend in a vertical direction; each first gate electrode structure is arranged in a first region of a semiconductor channel and surrounds the semiconductor channel; each second gate electrode structure is arranged in a second region of the semiconductor channel, and comprises a ring structure and at least one bridge structure, the ring structure surrounding the semiconductor channel, and the at least one bridge structure passing through the semiconductor channel and extending to an inner wall of the ring structure in a run-through direction; each covering layer is located in a spacing region between adjacent semiconductor channels; and the covering layer comprises a first communication hole extending in a vertical direction, and the top of the semiconductor channel and a part of a side wall thereof close to the top is exposed from the first communication hole.

JANG SEMYEONG (CN)
MOON JOONSUK (CN)
XIAO DEYUAN (CN)
HONG MINKI (CN)
LEE KYONGTAEK (CN)
CHIN JO-LAN (CN)

PCT/CN2022/101192

December 14, 2023

June 24, 2022

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CHANGXIN MEMORY TECH INC (CN)

H01L29/423; H01L29/66; H01L29/78

US20170309632A1	2017-10-26
US20150017767A1	2015-01-15
US20160204251A1	2016-07-14
US20190326395A1	2019-10-24
CN113078156A	2021-07-06

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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