SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR

WIPO Patent Application WO/2023/184571

A1

The present invention relates to a semiconductor structure and a preparation method therefor. The preparation method for the semiconductor structure comprises: providing a substrate, the substrate comprising an array region and a peripheral region that is connected to the array region; arranging a plurality of pads on the array region, an isolation trench being formed between adjacent pads; and forming a path layer to be etched on a sidewall of the isolation trench. In the described preparation method for the semiconductor structure, after the pads are formed, the path layer to be etched is formed on the sidewall of the isolation trench between the pads. The path layer to be etched can be in contact with a material layer to be etched in the array region. Therefore, after a flat surface is formed in the array region and the peripheral region, the path layer to be etched and the material layer to be etched can be sequentially removed. Since the peripheral region has a flat surface, a high-quality protective material layer can be formed on the surface thereof, preventing devices or material layers in the peripheral region from being damaged, thereby increasing the product yield.

WU RUNPING (CN)
KIM TAEGYUN (CN)
WON DAEJOONG (CN)
PARK SOONBYUNG (CN)

PCT/CN2022/086486

October 05, 2023

April 13, 2022

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CHANGXIN MEMORY TECH INC (CN)

H01L29/06

CN113675145A	2021-11-19
CN104900584A	2015-09-09
CN106504985A	2017-03-15
CN113937059A	2022-01-14
CN113690219A	2021-11-23
CN110098175A	2019-08-06
US20200020697A1	2020-01-16

ADVANCE CHINA IP LAW OFFICE (CN)

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