SEMICONDUCTOR STRUCTURE AND PREPARATION METHOD THEREFOR

WIPO Patent Application WO/2023/231152

A1

The present disclosure relates to a semiconductor structure and a preparation method therefor. The semiconductor structure comprises a substrate, which comprises a semiconductor base, wherein the semiconductor base is provided with first trenches extending in a first direction, and second trenches extending in a second direction, the first trenches intersect the second trenches so that a plurality of semiconductor columns are formed on the semiconductor base, the second trenches are filled with first dielectric layers, the tops of the semiconductor columns are provided with second dielectric layers, and side walls of the first trenches are provided with third dielectric layers; isolation layers, which are located in the semiconductor base below the first trenches, and extend in the second direction; and bit lines, which are located on the isolation layers, extend in the second direction, and are connected to the bottoms of the semiconductor columns. By means of the embodiments of the present disclosure, electrical leakage between the bit lines and the base can be effectively reduced.

XIAO DEYUAN (CN)
SHAO GUANGSU (CN)
QIU YUNSONG (CN)
JIANG YI (CN)
LIU YOUMING (CN)

PCT/CN2022/105726

December 07, 2023

July 14, 2022

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CHANGXIN MEMORY TECH INC (CN)

H01L23/538; H01L21/768

CN114121818A	2022-03-01
CN102054820A	2011-05-11
CN103515307A	2014-01-15
CN113644066A	2021-11-12
US8399342B2	2013-03-19

ADVANCE CHINA IP LAW OFFICE (CN)

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