Title:
SEMICONDUCTOR WAFER HOUSING CONTAINER
Document Type and Number:
WIPO Patent Application WO/2010/131291
Kind Code:
A1
Abstract:
A semiconductor wafer housing container is provided with wafer protection grooves (10) located in a deep-end wall (1b) of a container body (1). The grooves (10) have a cross-sectional shape of an undulation and are each formed such that a portion thereof opposed to an outer edge of each semiconductor wafer (W) is a groove bottom (10b) farthest away from an opening (1a) and such that each groove (10) has a greater opening width than the thickness of the semiconductor wafer (W). An imaginary line (Q) interconnecting the crests of the undulation is located on the inner side, or at the same positions as the outer edges, of the semiconductor wafers (W) facing the grooves (10). The construction provides the container with high impact resistance which makes the semiconductor wafers (W) housed in the container less likely to suffer damage even if a large impact due to dropping and careless handling of the container is applied to the container.
Inventors:
INOUE KAZUYA (JP)
Application Number:
PCT/JP2009/002073
Publication Date:
November 18, 2010
Filing Date:
May 13, 2009
Export Citation:
Assignee:
MIRAIAL CO LTD (JP)
INOUE KAZUYA (JP)
INOUE KAZUYA (JP)
International Classes:
H01L21/673
Foreign References:
| JP2005005525A | 2005-01-06 | |||
| JP2006303228A | 2006-11-02 |
Attorney, Agent or Firm:
MITSUI, KAZUHIKO (JP)
Kazuhiko Mitsui (JP)
Kazuhiko Mitsui (JP)
Download PDF:
Claims: