Title:
SEMICONDUCTOR WAFER SCRIBELANE STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/167841
Kind Code:
A3
Abstract:
An integrated circuit (IC) fabrication flow including a multilevel metallization scheme where one or more metal layer members (880-1 to 880-7) of a scribelane structure (893) are formed according to one or more design constraints. A total thickness of the metal layer members (880-1 to 880-7) of the scribelane structure (893) along a dicing path may be limited to a threshold value to optimize dicing separation yields in a dicing operation.
Inventors:
WEST JEFFREY (US)
STEWART ELIZABETH (US)
STEWART ELIZABETH (US)
Application Number:
PCT/US2023/014055
Publication Date:
October 19, 2023
Filing Date:
February 28, 2023
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC (US)
International Classes:
H01L23/00; H01L23/544; H01L23/58; H01L21/66; H01L23/31
Foreign References:
| US20080169533A1 | 2008-07-17 |
Attorney, Agent or Firm:
DAVIS, Valerie M. et al. (US)
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