Description

SENSE AMPLIFIER CIRCUIT FOR PARALLEL SENSING OF FOUR CURRENT LEVELS

TECHNICAL FIELD

The present invention relates to sense amplifier circuits for use in nonvolatile multi-bit memory integrated circuits.

BACKGROUND ART

In memory integrated circuits, sense amplifiers are used to detect and determine the data content of a selected memory cell. In EEPROM (Electronically Erasable Programmable Read Only Memories) and Flash memories, the sense amplifier serves two functions. Firstly, the sense amplifier precharges the bitline to a clamped value, and secondly, it senses the current flowing into the bitline, which depends on the memory cell state. Both the reliability, in terms of endurance and retention, and the performance depend greatly on the design of the sense amplifier.

A majority of integrated sense amplifier structures are based on a differential amplifier being used to compare the current coming from the selected memory cell to the current of a reference cell. The reference cells can be implemented in different ways, and are of different types. The reference cells are programmed one time only during the test of the memory, thus increasing the testing time. In order to ensure a good functionality of the sense amplifier, the ratio I _ce ii/Iref must be maintained high enough to take into account any process fluctuations on the memory and the reference cells, and any impact of the memory cycling on the memory cells. Moreover, it has been shown that the

speed performance and reliability of standard differential amplifier sense amplifiers are highly reduced for supply voltage values under 2 V. For example, U.S. Pat. No. 6,639,837 to Takano et al . discloses a current mirror circuit and a differential amplifier circuit for sensing multiple current levels stored in a memory cell .

Other types of sense amplifier structures are non-differential types that have nonsymmetrical circuits which detect and amplify signals which are generated by an accessed memory cell on a single amplifier input node. These types of sense amplifiers are often referred to as " single-ended. " Among the single-ended sense amplifiers of the prior art is U.S. Pat. No. 5,666,310 to Yu et al . , which discloses a single-ended sense amplifier that senses the current drawn by a memory array and changes a state of an output once a certain current has been reached. U.S. Pat. No. 5,013,943 to Hirose discloses a single-ended sense amplifier having a precharge circuit in order to lessen an effect of changing the bitline capacitance .

A trend in recent years is to design memory circuits that consume less power by decreasing power supply voltages of the memory device. As the power supply voltages decrease and the number of bits stored in a memory cell increase, it becomes more important that the sense amplifier be able to accurately sense very low current levels.

SUMMARY OF THE INVENTION

The present invention provides a single-ended sense amplifier having direct current amplification to accurately sense very low currents in a memory cell storing a plurality of bits, for example using low voltage CMOS nonvolatile memory devices. The sense

amplifier also includes an overshoot filtering circuit to filter glitches on a bitline and to control a discharge of the bitline.

The single-ended structure provides an advantage of eliminating a need to have a reference cell and comparator circuits as are commonly used in differential sense amp structures. This structure provides a savings in testing time and in an amount of die area used by the sense amplifier circuit. Additionally, the single-ended structure provides other advantages over the standard differential structures such as providing less sensitivity to mismatching and process variations, and providing improved access time at low supply voltages. By providing direct current amplification immediately following the current sensing, the sense amplifier of the present invention is faster and can sense very low currents compared to other single- ended sense amplifiers.

An exemplary embodiment of the present invention also has a precharge circuit to maintain a stable voltage on a bitline, and a sensing circuit coupled to the bitline for sensing an amount of current flowing into the bitline. A plurality of circuits are coupled to the sensing circuit including a plurality of direct current amplification circuits for amplifying the current sensed on the bitline, a plurality of current-to- voltage conversion circuits for converting the sensed current to a voltage, and a plurality of voltage amplification circuits for amplifying the voltage at the sense amplifier output. Outputs from each corresponding plurality of direct current amplification, current-to- voltage, and voltage amplification circuits are coupled to a logic decoder circuit to convert each possible current level within a given memory cell to a plurality of bits.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS . IA and IB are graphs of either two or four current levels per non-volatile memory cell and corresponding current trip points to detect stored logic value (s) .

FIG. 2 is an exemplary block diagram of the structure of the sense amplifier circuit of the present invention.

FIG. 3 is an exemplary electrical schematic diagram of the sense amplifier circuit of FIG. 2.

FIG. 4 is a table of exemplary memory cell current levels, current threshold detection levels, and decoded logic values.

DETAILED DESCRIPTION OF THE INVENTION

The present invention extends the current sensing approach of U.S. Patent No. 6,608,787 to memories having the capacity to store four or more current levels in a single memory cell. The current levels are sensed at the same time, allowing the storage of a plurality of data bits in a single memory cell .

Referring to FIG. IA, for a single bit memory cell, there are two current levels per cell and two current distributions, I _ce iii and Ic _e ii/ that correspond to two different programming data states. To discriminate between the two different memory states, a trip point I _tp is adjusted or established between the two current distributions I _C ein and I _ce ii ₂ • For example, a memory cell having a current value above the trip point I _tp stores a current value that represents a zero (0) logic value.

Correspondingly, a memory cell having a current value below the trip point It _p , stores a current value that represents a one (1) logic value.

In one embodiment, the current sensing and voltage conversion circuitry has a capability to

discriminate between four different current levels. Referring to FIG. IB, for an exemplary multiple bit memory cell, there are four current levels per memory cell and four current distributions, I _C eiiii/ Iceiiio, Ioeiioi/ and I _C eiioo _/ that correspond to four different programming conditions. Three different trip points I _tp i/ It _P 2, and I _tp3/ are needed between the four current distributions Iceiiii/ Iceiiio/ Iceiioi/ and Iceiioo- To discriminate between four different memory states, the three different trip points Itpi, It _P 2/ and It _P 3, are adjusted such that: I _tp i < Itp2 < I _t p3 ■ The first trip point I _tpl is adjusted between the first two current distributions I _ce iiii and I _C eiiio; the second trip point I _tp2 is adjusted between the two current distributions Iceiiio and Iceiioi; and the last trip point I _tP 3 is adjusted between current distributions I _ce iioi and

IcellOO •

In this example of a multiple bit memory cell, a memory cell having a current value I _C eiioo above trip point I _tP3 , represents a 00 logic value. Correspondingly, a memory cell having a current value Iceiioi between trip point I _tP 3 and trip point I _tp 2 represents a 01 logic value; a memory cell having a current value I _C eiiio between trip point I _t p2 and trip point I _tp i represents a 10 logic value; and a memory cell having a current value I _C eiin below trip point I _tp i represents a 11 logic value. Other multiple bit memory cells may include a greater number of potential current distributions (I _C eii) representing a greater number of logic values. For example, a memory cell having eight current values and seven trip points representing three possible bits per memory cell is readily envisioned.

With reference to FIG. 2, an exemplary sense amplifier 200 includes a precharge circuit 20, which functions to precharge and maintain a stable voltage on the bitline. The precharge circuit 20 receives a power

supply voltage Va _d 18 at a power input terminal 18 and a sense on/off signal at a signal input terminal 16 to activate the sense amplifier circuit. A sensing circuit 30 is coupled to a bitline and is used to sense the current flowing into the bitline. An overshoot filtering circuit 70 is coupled to the sensing circuit 30 in order to filter out glitches on the bitline. An output of the sensing circuit 30 is coupled to a plurality of direct current amplification circuits 40, 41, 42 that amplify the current sensed by the sensing circuit 30. The amplified currents are converted into voltages by current-to-voltage conversion circuits 5O ₇ 51, 52. The resulting voltages are then amplified by output amplification stages 60, 61, 62, which are coupled to a logic decoder circuit 80. The logic decoder circuit 80 derives a plurality of data bits based on the values presented by outputs 70, 71, 72, from the output amplification stages 60, 61, 62.

With reference to FIG. 3, the exemplary precharge circuit 20 consists of transistors 101, 102, 103, 202, 203 and resistor 300. Transistors 101, 102, and 103 are PMOS type transistors while transistors 202 and 203 are NMOS type transistors. Transistor 101 has a gate input coupled to the sense amplifier on/off signal input terminal 16, a source terminal coupled to the power supply voltage V _d d power input terminal 18, and a drain terminal coupled to the source terminal of PMOS transistor 102. Transistor 102 has a drain terminal coupled to the first end of resistor 300, and a gate terminal coupled to the gate of transistor 202.

Transistor 202 has a drain terminal coupled to the second end of resistor 300 and a source terminal coupled to ground potential 99. Transistor 103 has a gate terminal coupled to the gate terminal of transistor 202, a source terminal coupled to the drain terminal of transistor 101,

and a drain terminal coupled to the drain of transistor 203. Transistor 203 has a source terminal coupled to the gate of transistor 202 and a gate terminal coupled between the drain terminal of transistor 202 and the second end of resistor 300.

The sense amplifier circuit is controlled by an enable on signal input terminal 16. Transistor 201 is used to turn the sense amplifier off in stand by mode, or in a mode where there is no DC current. When the enable on signal input terminal 16 is at a high potential (at a high logic state or at Vdd) , there is no DC current flowing into the sense amplifier, and the sense circuitry is off. When the sense enable on signal input terminal 16 is at a low potential (at a low logic state or off) , the sense amplifier is turned on. The low signal turns on transistor 101 and turns off transistor 201. This allows current to flow through transistors 103, 203, and 210 and thus start the precharge circuit 20.

The precharge circuit 20 functions to precharge and maintain a stable voltage on a bitline 19. The precharge circuit also clamps the bitline 19 to a value lower than V _dd to limit read disturbs and to lower power consumption. The bitline 19 is coupled to the source terminal of transistor 203. The branch consisting of transistors 101, 103, and 203 must drive enough current to set the bitline 19 to its clamped voltage in a limited amount of time. The clamped precharge voltage is determined by the sizing of transistors 102 and 202 and the size of the coupled resistor 300. When the bitline 19 reaches the trip point of the transistors 102, 202 and the resistor 300 stage, a bias low line 25 goes low, turning off transistor 203, and thus turning off the precharge circuit 20.

The sense amplifier also includes an overshoot filtering circuit 70 consisting of PMOS transistor 104

and NMOS transistors 204, 205, and 212. Transistors 104 and 204 are coupled as an inverter with the source of transistor 104 being coupled to a power supply V _< j _d , the drain of 204 being coupled to the drain of transistor 204, the source of transistor 204 being coupled to the ground potential 993, and the gates of transistors 104 and 204 being coupled together and being supplied with a bias high signal at the gate terminal 75. The output of the 104, 204 inverter is coupled to the gate of transistor 205. Transistor 205 has a source terminal coupled to ground potential 993 and a drain terminal coupled to the source terminal of transistor 212. Transistor 212 has a drain terminal and gate coupled to the bitline 19. Due to the sense environment, overshoots can occur on the bitline 19 that can affect a normal sensing operation. The overshoot filtering circuit 70 serves to filter glitches on the bitline 19. For example, in the case of a positive glitch on the bitline, the bias high signal goes low which produces a high signal at the output of inverter 104, 204. This high signal turns on transistor 205 which discharges the glitch. Transistor 212 operates as a diode to limit the bitline 19 discharge when transistor 205 turns on. Compared to other structures that use a transistor as a diode, this circuit has an advantage of driving current in transistor 205 only if there is an overshoot on the bitline 19.

With continued reference to FIG. 3, in an exemplary embodiment, a sensing circuit 30 consists of NMOS transistor 210, and PMOS transistor 105. Transistor 210 serves to isolate bitline voltages from the gate level of transistor 105, which allows a voltage potential to be imposed by the precharge circuit 20 on the bitline 19. Transistor 201 has a drain terminal coupled to the gate terminal of transistor 210 and to the source

terminal of transistor 102 and to the first end of resistor 300. Transistor 201 also has a source terminal coupled to ground potential 99, and a gate terminal coupled to an enable on the signal input terminal 16 to detect a sense on/off signal. Transistor 210 has a gate terminal coupled to the drain terminal of transistor 201, a drain terminal coupled to the drain terminal and gate terminal of transistor 105 and to the gate terminals of transistors 106, 108, 110, and a source terminal coupled to bitline 19.

The sensing circuit is coupled to the plurality of direct current amplifier mirror circuits 40, 41, 42 consisting of PMOS transistors 106, 108 and 110. Transistors 105, 106, 108, and 110 have source terminals coupled to the power supply voltage V _dd - The drain terminals of transistors 106, 108 and 110 are correspondingly coupled to the drain terminal of NMOS transistors 206, 208, and 210 which comprise current-to- voltage conversion circuits 50, 51, 52. Optionally, transistor 206 has gate terminal 28 coupled to a sense mode enable signal. Transistors 206, 208, and 210 have source terminals coupled to the ground potential 99. Referring to FIG. IB and FIG. 3, the basic current to voltage and voltage amplification structure for detecting a first current trigger point I _tpl is composed of PMOS transistors 106 and 107, and NMOS transistors 206 and 207. Transistor 106 mirrors the cell current in transistor 105 multiplied by a multiplication factor of N. The first current in transistor 105 trigger point I _t pi, can be adjusted by varying the multiplication factor N and/or the size of transistor 106 to provide the desired current trigger point I _tp i • For example, the first current trigger point I _tp i can be adjusted by varying a width ratio between transistor 105 and transistor 106 when each has an equal length. The cell

current flowing in transistor 105 is directly amplified and is supplied to the drain of the low drive (low W/L value) transistor 206, resulting in a current-to-voltage conversion and resulting voltage V ₁ at node 58. Transistor 206 may be adjusted relative to transistor 105 or transistor 106, to vary a current to voltage conversion ratio and adjust current trigger point I _tp i.

Voltage V _x is amplified by a voltage amplification (inverter) circuit consisting of a PMOS transistor 107 and an NMOS transistor 207. Transistor 107 has a source terminal coupled to the power supply voltage V _dd and a drain terminal coupled to the drain terminal of transistor 207. Transistors 107 and 207 have gate terminals coupled to node 58 to receive the voltage V ₁ , and transistor 207 has a source terminal coupled to ground potential 99. Transistors 107 and 207 amplify the voltage V ₁ to produce an amplified voltage V ₂ at a first sense output OUTl 70. In order for V ₁ to reach the inverter trip point, enough current must flow into the drain of transistor 206, and the current flowing through the bitline 19 must be higher than a given value that corresponds to the first trip point I _t pi- Voltage V ₂ switches to ground when the V ₁ voltage reaches the inverter (transistors 107 and 207) trip point voltage. The basic current to voltage conversion structure of transistors 106, 206, 107, and 207 switches from 1 to 0 when voltage V ₁ reaches the inverter trip point V _t p. When V ₁ varies from a ground potential to V _tp , transistor 206, operating in a linear mode, exhibits a resistance and then switches into a saturation mode when the drain to source voltage (V _ds _ ₂ o6) is greater than a difference between a bias voltage Vbias applied to the gate of transistor 206 at node 28 and the threshold voltage V _th (where V _th is the threshold voltage of transistor 206; V _{ds 206} > V _b i _as - V _th ) • When transistor 206 is operating in

saturation mode, the device may be modeled as a current source in parallel with a very high equivalent resistance. Assuming that the conditions exist such that V _b i _as > V _t p - V _th/ transistor 206 will operate in a linear mode during the switching operation, resulting in the following expression for the current trip point I _tp , where μ represents the mobility of electrons, Cox represents the oxide capacitance per unit area, and W and L represent the width and length of transistor 206:

Itp — — μCox — (Fbias - Vt _n ) Ftp

The current trip point I _tp is adjusted by varying the factor N of the current mirror and/or the size of the transistor 206. Because the voltage trip point Vtp exhibits a linear variation with respect to the supply voltage V _dd , the current trip point I _tp exhibits a linear variation with respect to the supply voltage V _dd . When the bitline potential increases with the supply voltage V _dd/ the cell current I _Ce ii is expected to increase with the supply voltage V _dd , and a corresponding increase of the current trip point I _tp in the same order of magnitude is also expected.

In an exemplary embodiment, decreasing or canceling sensitivity to changes to the supply voltage V _dd is achieved by controlling the voltage level V _b i _as applied to the gate of transistor 206 at node 28 (as shown in FIG. 3) , to operate transistor 206 in a saturation mode during a sensing operation. As the voltage trip point V _tp increases with the supply voltage V _dd , transistor 206 increasingly operates in a saturation mode. A lower limit for the supply voltage V _dd may be determined by the current mirror transistor 106 and transistor 105 working in a saturation mode.

With reference to FIG. IB and FIG. 3, the basic structure of transistors 106, 206, 107, and 207 is repeated, with each successive structure having a different current trip point I _tp . Transistors 108, 208, 109, and 209 detect a second current trigger point I _tP2 / and transistors 110, 210, 111, and 211 detect a third current trigger point I _tP3 . In alternate embodiments, additional (successive) structures having different current trip points may be added to increase the number of bits stored in a memory cell . During a sensing operation, the basic structures of transistors (a first structure comprising 106, 206, 107, 207, a second structure comprising 108, 208, 109, 209, and a third structure comprising 110, 210, 111, and 211) operate at the same time in parallel, having different current trip points Itpi, It _P 2/ and It _P 3 • Because a plurality of the basic structures of transistors operate in parallel, an improvement in operating speed is obtained.

The current trip points Itpi, It _P 2, and It _P 3 are adjusted, using a multiplication factor N for each circuit. The multiplication factor N may be adjusted by changing the size or dimension ratios of an adjusted transistor relative to the size and characteristics of transistor 206 for each of the basic structures described above. For I _tp2 / transistors 108 and 208 are adjusted; for I _tP 3/ transistors 110 and 210 are adjusted; each adjustment provides operational trip points as described supra with reference to exemplary FIG. IB. For example, the sizing of transistor 106 is equal to a multiplier Ni multiplied by the sizing of transistor 105; the sizing of transistor 108 is equal to a multiplier N ₂ multiplied by the sizing of transistor 105; and the sizing of transistor 110 is equal to a multiplier N ₃ multiplied by the sizing of transistor 105 such that Ni > N ₂ > N ₃ . Each of the basic structures having been adjusted for

different trip points and provide trip point outputs OUTl 70, 0UT2 71, and OUT3 73.

With further reference to FIG. 3, logic decoder 80 is coupled to the voltage amplification circuit outputs OUTl 70, 0UT2 72, OUT3 73, of the voltage amplification circuits 60, 61, 62. The switched states of the voltage amplification circuit outputs OUTl 70, 0UT2 71, 0UT3 72 correspond to the amount of current flowing in a bitline. Each output is correspondingly related to the current trigger points Itpi, Itp2, and I _tp 3 as shown in FIG. IB. The logic decoder circuit 80 derives a plurality of data bits BITO, BITl, on the logic decoder output lines 81, 82, based on the sensed current from a memory cell and the output from each of the first, second, and third structures of transistors described above .

Referring to FIG. IB and FIG. 4, in an exemplary embodiment, for a memory cell current I _ce ii that is less than the first current trip point, none of the trip points Itpi, Itp2, and I _tP3 will trip, and the outputs

OUTl 70, OUT2 71, and OUT3 72 will be equal to one or at a high logic state. As the sensed memory cell current I _ce ii increases, the basic structure of transistors, each having different current trip points Itpi, It _P 2, and I _tP 3, will trip depending on the value of the cell current I _ce ii- For example, when the memory cell current I _Ce ii is between the first I _tp i and second I _tP2 trip points, node 58 rises above the voltage trip point V _tp of the inverter 60 and the output OUTl 70 from transistors 106 and 206 will switch to a low logic state. When the memory cell current I _ce ii exceeds the highest trip point Itp3 , all of the outputs OUTl 7O ₇ 0UT2 71, and OUT3 72 will be at a low logic state .

Referring to FIG. 4, the logic decoder provides two bits BITO, BITl, depending on a state of each output

OUTl 70, OUT2 71, OUT3 72, that correspond to three different current trip points It _P i, Itp2/ and It _P 3, discriminating between four different memory cell current levels. When the outputs OUTl 70, 0UT2 71, 0UT3 72 are high, the two bits stored in a memory cell are 11. A memory cell having a current value I _ce ii below trip point I _tp i represents a 11 logic value; a memory cell having a current value I _ce ii between trip point I _tp i and I _tP 2 represents a 10 logic value; a memory cell having a current value I _ce ii between trip point I _tp 2 and I _tP 3 represents a 01 logic value; and a memory cell having a current value I _C eii above trip point I _tP 3 represents a 00 logic value. Alternate embodiments may logically decode the outputs from the sense circuit to provide other combinations of bits. Other embodiments of a multiple bit memory cell may include a greater number of I _ce ii current distributions and a sense circuit having a greater number of circuit elements and current trip points that represent a greater number of stored logic values. For example, a memory cell may store eight current values and a sense circuit may support seven trip points representing three possible bits of storage per memory cell .

The above described sense amplifier provides many advantages including a high robustness to process variations, improved access time at low power supply voltages, and a full and easy implementation using low voltage CMOS devices. Those of skill in the art will recognize that the invention can be practiced with modification and alteration within the spirit and scope of the appended claims and many other embodiments will be apparent to those of skill in the art upon reading an understanding the above description. For example, the circuit devices are described in terms of NMOS and PMOS transistors. However, one skilled in the art would

recognize that other types of transistors may be supplemented while still achieving the same overall effect. The description is thus to be regarded as illustrative instead of limiting.