Title:
SENSE AMPLIFIER FOR COMPLEMENTARY OR NON-COMPLEMENTARY DATA SIGNALS
Document Type and Number:
WIPO Patent Application WO1999005782
Kind Code:
A3
Abstract:
A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complementary data signals at their differential inputs. In the altered mode, the mode control circuit couples a reference voltage to the second inputs of the sense amplifiers in the first stage so that the sense amplifiers compare a respective data signal to the reference voltage. The mode control circuit also alters the operation of the second stage. In the normal mode, the mode control circuit couples an output signal from the other sense amplifier in the first stage to a respective second input of each sense amplifier in the second stage so that the sense amplifiers receive at their differential inputs both of the complementary output signals from each sense amplifier in the first stage. In the altered mode, the mode control circuit couples a data signal to the respective second input of each sense amplifier in the second stage so that the sense amplifiers compare an output signal from a respective sense amplifier in the first stage to a respective data signal.
Inventors:
MANNING TROY A
MARTIN CHRIS G
MARTIN CHRIS G
Application Number:
PCT/US1998/014998
Publication Date:
April 15, 1999
Filing Date:
July 20, 1998
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G11C7/06; (IPC1-7): G11C7/06; G11C29/00
Foreign References:
| US5029330A | 1991-07-02 | |||
| EP0828252A2 | 1998-03-11 | |||
| EP0840328A2 | 1998-05-06 |
Other References:
KOICHIRO ISHIBASHI ET AL: "A 6-NS 4-MB CMOS SRAM WITH OFFSET-VLTAGE-INSENSITIVE CURRENT SENSE AMPLIFIERS", IEICE TRANSACTIONS ON ELECTRONICS, vol. E78-C, no. 6, 1 June 1995 (1995-06-01), pages 728 - 733, XP000524431
TADAHIRO KURODA ET AL: "AUTOMATED BIAS CONTROL (ABC) CIRCUIT FOR HIGH-PERFORMANCE VLSI'S", IEICE TRANSACTIONS ON ELECTRONICS, vol. E75 - C, no. 4, 1 April 1992 (1992-04-01), pages 539 - 545, XP000301687
TADAHIRO KURODA ET AL: "AUTOMATED BIAS CONTROL (ABC) CIRCUIT FOR HIGH-PERFORMANCE VLSI'S", IEICE TRANSACTIONS ON ELECTRONICS, vol. E75 - C, no. 4, 1 April 1992 (1992-04-01), pages 539 - 545, XP000301687
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