Title:
SEQUENTIAL NIBBLE BURST ORDERING FOR DATA
Document Type and Number:
WIPO Patent Application WO2003050690
Kind Code:
A3
Abstract:
A memory device is comprised of a plurality of arrays of memory cells and peripheral devices for reading information out of and for writing information into the memory cells. The peripheral devices include a decode circuit responsive to a first portion of address information for identifying an address and is further responsive to a second portion of the address information for identifying an order. The address may by a read address or a write address, and the order may be the order for reading data or writing data, respectively. The peripheral devices may also include a read sequencer circuit or both a write sequencer circuit and a read sequencer circuit for reordering bits to be read or written, as the case may be, in response to another portion of the address information. The necessary address information is routed to the sequencer circuits by an address sequencer. Methods of operating such a memory device are also disclosed.
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Inventors:
JANZEN JEFFERY W
Application Number:
PCT/US2002/038572
Publication Date:
January 29, 2004
Filing Date:
December 05, 2002
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G06F12/02; G06F12/00; G06F13/00; G06F13/16; G11C7/10; G11C11/401; G11C11/407; G11C11/408; (IPC1-7): G11C7/10
Foreign References:
| US6240047B1 | 2001-05-29 | |||
| US5815460A | 1998-09-29 | |||
| US5953278A | 1999-09-14 | |||
| US20010026478A1 | 2001-10-04 |
Other References:
See also references of EP 1454322A2
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