Title:
SERIAL DATA RECEIVING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1990/010903
Kind Code:
A1
Abstract:
The serial data receiving circuit of the invention comprises a most significant bit input detecting circuit (20) which produces a predetermined control signal in synchronism with the reception of the most significant bit of serial data of two's complement notation, and a data converting circuit (30A) which performs sign-extension of the serial data to output the extended data as parallel data while said control signal is active, and shifts the serial data from the least significant bit to the most significant bit to output them as parallel data while the control signal is not active. There is further provided a sign-extended data processing circuit (40) that converts the serial data into sign-extended data according to a formatting control signal. Hence, there are obtained parallel data in the two's complement notation from any of serially inputted data whose numbers of input bits are variable and which are of two's complement notation, of offset binary, and of straight binary.
Inventors:
ISHIDA HISAKI (JP)
Application Number:
PCT/JP1990/000331
Publication Date:
September 20, 1990
Filing Date:
March 14, 1990
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD (JP)
International Classes:
G06F5/00; H03M9/00; (IPC1-7): G06F5/00
Foreign References:
| JPS55976A | 1980-01-07 |
Other References:
See also references of EP 0417314A4
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