Title:
SHIFT REGISTER AND DISPLAY DEVICE PROVIDED WITH SAME
Document Type and Number:
WIPO Patent Application WO/2012/008186
Kind Code:
A1
Abstract:
Disclosed is a shift register (10) that connects an m number of multiple levels with unit circuits (11) that have a shift unit (12) and three buffer units (13r, 13g, 13b), and outputs three signals from each level, totaling an output of 3m signals. The m number of shift units (12) perform shift operation and output a first signal (Y) from each level. When a clock signal (CK) level is high, the first signal (Y) is at a higher high level than usual due to bootstrapping. The buffer unit (13r) controls the output signal (YR) at a high level based on a buffer control signal (CR) and the first signal (Y). A buffer control circuit (7) controls each buffer control signal (CR, CG, CB) at a high level for a shorter time than the half-cycle of the clock signal. As a result, the shift register has a low circuit volume and low power consumption.
Inventors:
YAMAMOTO KAORU
OGAWA YASUYUKI
OGAWA YASUYUKI
Application Number:
PCT/JP2011/058555
Publication Date:
January 19, 2012
Filing Date:
April 04, 2011
Export Citation:
Assignee:
SHARP KK (JP)
YAMAMOTO KAORU
OGAWA YASUYUKI
YAMAMOTO KAORU
OGAWA YASUYUKI
International Classes:
G11C19/28; G09G3/20; G09G3/36; G11C19/00
Domestic Patent References:
| WO2010050262A1 | 2010-05-06 |
Foreign References:
| JP2008140490A | 2008-06-19 | |||
| JP2010092545A | 2010-04-22 | |||
| JPH0282295A | 1990-03-22 | |||
| JP2006058770A | 2006-03-02 | |||
| JP2005234057A | 2005-09-02 |
Attorney, Agent or Firm:
SHIMADA, AKIHIRO (JP)
Akihiro Shimada (JP)
Akihiro Shimada (JP)
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Claims: