Title:
SIGMA-DELTA CONVERTERS AND METHODS FOR ANALOG-TO-DIGITAL CONVERSION
Document Type and Number:
WIPO Patent Application WO/2010/132619
Kind Code:
A3
Abstract:
A switched capacitor sigma-delta modulator or another analog-to-digital converter (ADC) uses chopper stabilization. Chopping clock transitions are performed during non-active periods of the sampling clock phases, reducing disturbance of the circuit caused by chopping and increasing the time available for settling of the circuit given a particular sampling frequency. An asynchronous state machine may govern sampling and chopping clock transitions. In embodiments, inactive transition of a first sampling clock causes inactive transition of a second chopping clock, which in turn causes active transition of a first chopping clock. The next inactive transition of the first sampling clock causes inactive transition of the first chopping clock, which causes an active transition of the second chopping clock.
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Inventors:
GROENEWOLD GERRIT (US)
Application Number:
PCT/US2010/034622
Publication Date:
December 29, 2010
Filing Date:
May 12, 2010
Export Citation:
Assignee:
QUALCOMM INC (US)
GROENEWOLD GERRIT (US)
GROENEWOLD GERRIT (US)
International Classes:
H03M3/00; H03M3/02
Other References:
YI-GYEONG KIM ET AL: "A 105.5 dB, 0.49 mm2 Audio Î GBP Î modulator using chopper stabilization and fully randomized DWA", CUSTOM INTEGRATED CIRCUITS CONFERENCE, 2008. CICC 2008. IEEE, IEEE, PISCATAWAY, NJ, USA, 21 September 2008 (2008-09-21), pages 503 - 506, XP031361509, ISBN: 978-1-4244-2018-6
Attorney, Agent or Firm:
XU, Jiayu (5775 Morehouse DriveSan Diego, Califonia, US)
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