Background of the invention Signal conversion or modulation has become a somewhat broad discipline covering several different techniques, each having fundamental different functions and performance. One of these techniques is the sigma-delta concept. The sigma-delta concept is very attractive for many purposes due to its basically integral and differential linearity combined with a quite simple basic architecture. Moreover, the concept involves more or less refined techniques dealing with distribution of noise within and especially outside the signal processing band.

Sigma-delta converters have become widespread, especially within the field of audio applications.

A problem of the sigma-delta modulators is, nevertheless, that the ever increasing requirements to high resolution, high dynamic range and low noise are difficult to meet.

The resulting technical development has focused on quite complicated derivatives of the sigma-delta concept such as high-order feedback loops and multi-bit feedback. A problem with the generally accepted techniques, especially the multi-bit technique, is that it compromises e. g. linearity unless very careful matching of the multi-bit feed-back signal is established which makes the technique poorly suited for in a high speed

feedback loop. Turning to the high order sigma-delta converters, the basic technique deals with minimising signal noise inside the signal-band without compromising the linearity. A serious problem is, nevertheless, that the noise of the converter grows with the dynamic range, and consequently the immediate answer is to increase the order of the converter.

It is an object of the invention to maintain the advantageous features of a sigma-delta converter and at the same time reduce critical noise.

Summary of the invention When, as stated in claim 1, delta is differential adapted to the input and/or output signal, an advantageous sigma- delta modulator has been obtained. Thus, a sigma-delta converter according to the invention provides the possibility of very low noise performance when noise is most critical. When adapting the delta value to the input and/or output signal, delta may be minimised to the actual input and not only to worst case dynamic range.

Basically, the invention introduces a new approach within the field of sigma-delta converters, as the invention introduces a non-fixed A value and consequently variable quantisation noise. The quantisation noise may thus be acceptable even if relatively high, in situation where a large dynamic range is required.

On the other hand, if the signal levels are low, the quantisation level A may be reduced for the purpose of reducing quantisation noise.

A fundamental approach to the invention is that low signal level variations imply very strict requirements of low noise, while significant variations in the input signal levels may ease the requirements to low noise due to the fact that the utility signal masks the noise.

It should be noted that the total RMS noise is a function of the delta value, i. e. the quantisation levels of the feed-back modulation loop, and consequently an adaption of delta to the input signal will reduce the induced noise.

It should moreover be noted that the technique of the invention basically offers linearity over the entire dynamic range.

In particular, it should be noted that a first order, one-bit sigma-delta converter according to the invention maintains linearity as a regular one-bit converter, while still obtaining a variable range.

It should moreover be noted that delta in a sigma-delta modulator represent the analogue quantisation step-size in the feed-back loop (s).

According to the invention, delta defines the analogue step size of the analogue feed-back (s) of the sigma- delta converter.

When, as stated in claim 2, delta is established on the basis of a measurement of a measuring period (MP) of the input and/or output signal, a further advantageous preferred embodiment of the invention has been obtained.

When measuring over a period a reliable modulator concept has been obtained. Of course, the measuring period should be adapted to the knowledge of the form and content of the input signal. In a mobile communication system such as GSM, this period may e. g. be the length of a TDMA time slot, i. e. typically larger than 1 ms, while the base band is in the order of 200-1000 kbit/s.

When adapting delta to the input signal variation over a period, it is e. g. possible to maintain a high delta if the signal varies significantly, while keeping distortion due to saturation low. Correspondingly, delta may be kept low when small signal variations are expected, thus minimising the quantisation noise significantly in a simple manner.

When, as stated in claim 3, said measuring period (MP) of the input and/or output signal is fixed, a further advantageous embodiment of the invention has been obtained.

When, as stated in claim 4, said measuring period (MP) of the input and/or output signal is 577 J. s, corresponding to a TDMA time slot in a GSM system, a further advantageous embodiment of the invention has been obtained.

It should be noted that this technique is very attractive in relation to communication systems having a coding establishing a somewhat conservative signal. Thus, a GSM is conservative over a relatively long period, and a sigma-delta modulator according to the invention may

easily be adapted to and utilised advantageously in GSM systems.

When, as stated in claim 5, the power level of a previous time slot is a measure parameter, a further advantageous embodiment of the invention has been obtained.

Especially because the power level of a time slot in a GSM system normally is kept almost constant.

When, as stated in claim 6, delta is constant during the measuring period, a further advantageous embodiment of the invention has been obtained.

It should be mentioned that a sigma-delta modulator according to the embodiment of the invention is adapted to a period of signal components of the input signals instead of carrying out discrete hunting of a specific discrete analogue input value. When measuring over a time period longer than the input information rate, and maintaining an adapted delta value over a period the linearity of the converter offers high linearity over the whole dynamic range, resulting in a gain of dynamically range.

When, as stated in claim 7, said measuring period (MP) is larger than an input information rate (PI), a further advantageous embodiment of the invention has been obtained When, as stated in claim 8, a current delta is established in dependency of a currently measured output signal and at least one previously measured output

signal, a further advantageous embodiment of the invention has been obtained.

When, as stated in claim 9, said time period is adapted to the time constant of the human ear, very attractive and interesting performance qualities of a sigma-delta converter has been obtained due to the fact a slight overdrive of the converter for a period would be acceptable, particularly in within the field of audio.

This is due to the fact that the human ear will not recognise short period overdrives of the converter caused by the current delta value being too small.

A preferred time period would be less than 20 ms, preferably about 10 ms.

It should be noted that the time constant adapted to the measuring period may of course be shorter, as long as the dimensioning of the overall modulator ensures that the delta value has been adapted to the input signal level before the human ear recognises any distortion. The total period may e. g. comprise some measuring periods or a sequence of measuring periods.

When, as stated in claim 10, at least one feed-back loop, said at least one feed-back loop having an analogue step- size of delta, said delta being variable and adapted to the input and/or output signal, a further advantageous embodiment of the invention has been obtained.

When, as stated in claim 11, the sigma-delta modulator wherein delta is differential adapted to the input and/or output signal with the use of at least one algorithm, a

advantageous embodiment of the invention has been obtained.

The word"algorithm"in connection with the invention may be defined as any procedure or rule to convert one or more input and/or output signal to a delta. An example of an algorithm could be one or more mathematical formulas.

Another example could be a table or a record containing values for each input and/or output signals, where a form of treatment takes place between at least two signals to derive at one or more delta values.

When, as stated in claim 12, the established delta Ak of a current time measuring period k is determined as Ak= max ({Uk-l}) 1, 5 where {Uk1} is a set of amplitude samples of a previous measuring period, a further advantageous embodiment of the invention has been obtained.

This is especially advantageous since a factor of 1,5 allows a 3dB margin before saturation.

The figures The invention will be described in details below with reference to the drawings in which fig. 1 shows a prior art sigma-delta modulator,

figs. 2a and 2b illustrate the output of a prior art one-bit sigma-delta modulator, figs. 3a and 3b illustrate the output of a multi-level prior art sigma-delta modulator, figs. 4a and 4b illustrate the output of a one-bit sigma-delta modulator according to the invention, fig. 4c illustrates a one-bit quantisation method according to the invention, figs. 5a and 5b illustrate a one-bit quantisation method according to the invention, fig. 6 shows a sigma-delta converter according to the invention, and where fig. 7 shows a number of measuring periods according to the invention.

Detailed description Fig. 1 illustrates the basic properties of a prior art first order one-bit sigma-delta modulator.

For explanatory purposes of the invention, the functioning of a prior art modulator will be described in details below.

The sigma-delta modulator comprises an input for an analogue input x (t). The input is summed to a feed-back signal in a summing unit 11. The resulting sum is fed to

an analogue filter in the form of an integrator 12. The output of the integrator is fed to a digital output y (n) via a quantizer 13.

The digital output signal is moreover fed back to the summing unit 11 via a one bit D/A converter 14 and subsequently subtracted from the input signal. The subtracted signal will subsequently be integrated in the integrator 12, and the difference between the feed-back signal and the input signal will be integrated, etc.

Basically, the sigma-delta modulator digitises an analogue signal with a low one bit resolution at a very high sampling rate.

In order to obtain a decrease in noise within the operational frequencies of the modulator, current oversampling techniques spread the present quantisation noise over a broader frequency spectrum. Subsequently, a digital low pass filter may remove a substantive part of the quantisation noise, and finally the signal may be decimated on the digital output of the modulator. These techniques are well-known within the art.

Moreover, a prior art sigma-delta modulator deals with an additional noise reducing facility, as a so-called noise shaping shapes the present quantisation noise in such a way that noise is non-uniform with respect to the frequency domain. More specifically, the majority of the quantisation noise may be moved without the domain of the low pass filter. Consequently, the digital filter may remove a substantive part of the noise in a comfortable and easy way by means of the above-mentioned digital

filter. These techniques are also well-known within the art, and are one of the main aspects of a high-order sigma-delta modulator. A reasonable assumption is that the quality of the noise shaping improves with higher- order modulators.

The shown prior art sigma-delta converter has a first- order feed-back loop and may thus take advantage of this noise shaping in its most primitive form.

A problem with the shown sigma delta converter is nevertheless that noise, such as the above-mentioned RMS quantisation noise of A2/12 becomes to dominating within the operating frequency spectrum under certain circumstances.

This problem may be illustrated by means of fig. 2 showing the output of the above-mentioned first-order sigma-delta modulator as a response of a ramp input.

In fig. 2a an analogue input signal x (t) is modulated between two levels A/2.

Obviously, if the ramp x (t) represents an input signal having a very high dynamic range, the quantisation noise may become critical, as the total RMS noise of A2/12 increases with the square of the A.

One of two mainstreams within the field of noise reduction in sigma-delta converters is the above- mentioned noise shaping technique involving high order feed-back loops. High order sigma-delta modulators

allocates an even greater portion of the above-mentioned quantisation noise outside the frequency band of interest. A problem of this technique is, nevertheless, that higher order modulator loops are difficult to analyse and stabilise. Loops in excess of two are generally difficult to stabilise and the simple linear model is no longer accurate. Low cost modulators are generally hardly obtainable within this technique.

Another technique deals with the above-mentioned problem in a basically different way, as the technical efforts concentrate on a reducing the total quantisation noise instead of moving the noise to other spectral components.

This technique includes multilevel quantisation resulting in minimising of the quantising noise.

Fig. 2b illustrates the above-mentioned problem of saturation, as the input x (t) now has been inclined and overdrives the input. The resulting overdrive has been illustrated by arrows, Sat.

Fig. 3a shows an example of the output of such a sigma- delta multi-level modulator fed by an analogue ramp input signal x (t).

If a signal exceeds a certain max. level the quantisation may be implemented between other quantisation levels. A multi-level sigma-delta converter basically provides the possibility of having a relatively small quantisation level A over the total dynamic range.

The advantage of the above-mentioned multi-level technique is that a relatively small quantisation level A influences and reduces the total noise over the total dynamic directly.

Another problem with the above-mentioned technique is nevertheless that the D/A converter establishing the quantisation levels introduces both critical differentional and integral non-linearities. This non- linearity may be compensated for when carefully dimensioned and calibrated to a certain degree, but the technique will never fulfil the needs of the sigma-delta concept, as it should be noticed that the multilevel quantisation must be established at very high frequencies due to the oversampling.

Moreover, fig. 3b illustrates the scenario of a modulator being overdriven by the input signal x (t). Again the resulting saturation is illustrated by arrows, Sat.

Figs. 4a and 4b show the output of a sigma-delta modulator according to the invention when the modulator is fed by an analogue ramp signal corresponding to the signal x (t) of figs. 2a, 2b, 3a and 3b.

When adapting delta to the input signal variation over a period, it is e. g. possible to maintain a high delta if the signal varies significantly, while keeping distortion due to saturation low. Correspondingly, delta may be kept low when small signal variations are expected, thus minimising the quantisation noise significantly in a simple manner.

Turning now to fig. 4c, the quantisation method of figs.

4a and 4b has been illustrated. A=l represents the variable setting of A according to fig. 4b, and A=5 represents the variable setting of A according to fig.

4a.

Figs. 5a and 5b illustrate a variable setting of A in a multi-modulator aaccording to the invention.

Fig. 5a illustrates a multi-level modulator having a three bit resolution, i. e. eight possible quantisation steps. These quantisation steps are illustrated on the vertical axes. The distance between the quantisation step is determined as A/2, where n represents the number of bits. As the number of bits is three, the distance between the steps is 1/8, if A is assumed to be 1.

Turning now to fig. 5b, the A has been modified to the value A=S according to an applied adaptive algorithm. The resulting step size will consequently be modified according to A. Hence, the distance between the levels is now 1/16.

It may consequently be appreciated that the A adaptive approach of the invention may be equally applied to both one-bit and multi-level sigma-delta modulators.

Fig. 6 illustrates the principle of a first order sigma- delta converter according to the invention.

Initially, it should be emphasised that the illustrated embodiment of the invention only refers to one of several classes of sigma-delta modulators in which the teaching of the invention may be utilised. Thus, the adaptive approach of delta according to the invention may be used in e. g. high order sigma-delta converters and/or multilevel sigma-delta modulators.

The sigma-delta modulator comprises an input for an analogue input x (t). The input is summed to a feed-back signal in a summing unit 61. The resulting sum is fed to an analogue filter in the form of an integrator 62. The output of the integrator is feed to a digital output y (n) via a level controlled quantizer 63. The level-controlled quantizer establishes an adapted feed-back quantisation on the basis of the input signal. In this case an adaption control 65 establishes a measurement of the input signal of the modulator circuit on the basis of e. g. an average RMS value over a measuring period. Each measure is temporarily stored, and each current measure is compared to the previous measure of the previous period. It should be noted that the measuring period is larger than the input information rate or in other words, it should be longer than the input signal period (1/f). A time period of more than hundred times the information rate is sufficient to ensure proper linear properties of the sigma-delta modulator. This time period is typically one ms or longer, while the baseband bitrate is within the range of 200-1000 kbit/s. Moreover, the oversampling ratio will reduce the influence of the adaptive decrease in linearity. In a GSM system this can be done by using the power level from the previous time slot as the adaptive parameter. This is due to the fact

that the power level of a GSM time slot is kept almost constant.

It should be noted that the established delta in the quantiser 64 is kept at a constant during the entire measuring period.

According to one embodiment of the invention illustrated in fig. 7, the established delta Ak of a current time measuring period k may e. g. be determined as Ak= max ({Uk l}) 1t 5 where {U-i} is a set of amplitude samples of a previous measuring period. A factor of 1,5 allows a 3dB margin before saturation. In a GSM system a measuring period of 577 ps, corresponds to a TDMA time slot.

It should be noted that the above-mentioned technique is very attractive in relation to e. g. communication systems having a coding establishing a somewhat conservative signal. Thus, a GSM is conservative over a relatively long period, and a sigma-delta modulator according to the invention may easily be adapted to and utilised advantageously in GSM systems.

It should be noted that a sigma-delta modulator according to the invention may be applicable to both an A/D- converter and a D/A-converter.

Finally, it should again be emphasised that the adaptive establishment of a delta according to the invention may

be applicable by not only a first order one bit sigma- delta modulator. On the contrary, the advantages may be combined with higher order one and multi-bit sigma-delta modulators, thus obtaining a synergy of both noise shaping, linearity and noise reduction.