Field of the Disclosure The present disclosure relates to a signal generation device, a wireless communication device comprising the signal generation device, and a method of operating a signal generation device, and has application to, in particular, but not exclusively, apparatus for wireless communication. Background to the Disclosure

The project leading to this application has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No 671563.

Wireless communication equipments employ phase locked loops (PLLs) for signal generation. A typical PLL comprises a voltage controlled oscillator (VCO) whose signal is divided, and the phase of the divided signal is compared in a phase detector, or phase frequency detector, to that of a reference signal to generate a difference signal. The difference signal controls a charge pump such that a current is pushed or pulled by the charge pump into a loop filter that delivers a control voltage for decreasing or increasing the frequency of the VCO.

In wireless communication systems, very high data rates need to be supported and increasingly higher frequency bands are being employed, including the mm-wave spectrum. In the mm-wave spectrum, higher reference frequencies can be used to avoid the use of a very high division ratio in a PLL. This can degrade the noise performance of the PLL because noise generated by a reference frequency generator is amplified by a frequency divider division ratio. A surface acoustic wave (SAW) resonator can be used for generating high reference frequencies, which can contribute to reducing the division ratio.

The PLL bandwidth is usually chosen to minimize phase noise. A higher frequency VCO has an acceptably low phase noise at a lower relative frequency offset from the carrier, and therefore, in order to limit the noise, a reduced relative bandwidth is chosen for a PLL operating at higher frequencies. In addition, the gain of the VCO in an mm-wave PLL is extremely high, and in a fully integrated design with all loop filter components on-chip, limiting the maximum value of capacitances, the charge pump current must be reduced to limit the bandwidth. When changing the operating frequency of the PLL, the combined effects of the reduced PLL bandwidth and the reduced current in the charge pump cause the PLL loop to react slowly. If a frequency step in the divided signal is large, cycle slipping occurs due to limited dynamic range of the phase detector or phase frequency detector.

Consequently, although the PLL still converges, the settling time is considerably increased. Moreover, wireless communication systems operating at high frequencies use fast frequency hopping, and a fast settling time is therefore required in the PLL.

There is a requirement for improvements in signal generation devices. Summary of the Preferred Embodiments

According to a first aspect there is provided a signal generation device comprising: a variable frequency oscillator configured to generate an output signal having an output frequency dependent on an oscillator control signal;

a first frequency division stage configured to generate from the output signal a first comparison signal having a first comparison frequency equal to the output frequency divided by a first divisor, wherein the first divisor is variable;

a second frequency division stage configured to generate from a reference signal a second comparison signal having a second comparison frequency equal to the frequency of the reference signal divided by a second divisor, wherein the second divisor is variable;

a comparator configured to generate a difference signal dependent on a phase difference between the first and second comparison signals;

a charge pump configured to generate a pulsed signal dependent on the difference signal, wherein a gain of the charge pump is variable;

a filter configured to generate the oscillator control signal by filtering the pulsed signal; and

a controller configured to, in response to an indication of a desired change in the output frequency from an initial frequency to a final frequency, control the first and second divisors such that the signal generation device switches from an initial mode in which the output signal has the initial frequency to a final mode in which the output signal has the final frequency through an interim mode in which the first and second divisors are larger than in the final mode by a common multiplier, and control the gain of the charge pump to be higher in the interim mode than in the final mode.

According to a second aspect there is provided a method of operating signal generation device comprising: generating an output signal having an output frequency dependent on an oscillator control signal;

generating from the output signal a first comparison signal having a first comparison frequency equal to the output frequency divided by a first divisor, wherein the first divisor is variable;

generating from a reference signal a second comparison signal having a second comparison frequency equal to the frequency of the reference signal divided by a second divisor, wherein the second divisor is variable;

generating a difference signal dependent on a phase difference between the first and second comparison signals;

generating in a charge pump a pulsed signal dependent on the difference signal, wherein a gain of the charge pump is variable;

generating the oscillator control signal by filtering the pulsed signal; and in response to an indication of a desired change in the output frequency from an initial frequency to a final frequency, controlling the first and second divisors such that the signal generation device switches from an initial mode in which the output signal has the initial frequency to a final mode in which the output signal has the final frequency through an interim mode in which the first and second divisors are larger than in the final mode by a common multiplier and controlling the gain of the charge pump to be higher in the interim mode than in the final mode.

The use of an interim mode in which the first and second divisors are larger by a common multiplier, and the gain of the charge pump is higher than in the final mode, can enable the settling time of the signal generation device to be reduced when switching to a different output frequency without degrading, or with reduced degradation to, the bandwidth and phase margin of the signal generation device.

Preferably, the gain of the charge pump in the interim mode may be higher than in the final mode by a gain factor equal to the common multiplier. In other embodiments, the gain of the charge pump in the interim mode may higher than in the final mode by a gain factor equal to the common multiplier within one of: twenty percent, ten percent, five percent, two percent, one percent. These features can enable improved performance of the signal generation device.

In some embodiments, the first frequency division stage may comprise:

a first frequency divider configured to generate a first divided signal by dividing the output signal by a first division factor dependent, in the initial mode, on the initial frequency and, in the interim and final modes, on the final frequency; a second frequency divider configured to generate a second divided signal by dividing the first divided signal by a second division factor equal to the common multiplier; and

a first selection stage configured to provide the first comparison signal as a selected one of the first divided signal and the second divided signal, wherein the controller is configured to control the first selection stage to select the first divided signal in the initial and final modes and to select the second divided signal in the interim mode.

Likewise, in the method, generating the first comparison signal may comprise: generating a first divided signal by dividing the output signal by a first division factor dependent, in the initial mode, on the initial frequency and, in the interim and final modes, on the final frequency;

generating a second divided signal by dividing the first divided signal by a second division factor equal to the common multiplier;

providing the first comparison signal as a selected one of the first divided signal and the second divided signal, wherein in the initial and final modes the first divided signal is selected, and in the interim mode the second divided signal is selected.

These features enable low power consumption by enabling the dividing of the first divided signal by the second division factor to be suspended during the initial and final modes.

In other embodiments, the first frequency division stage may comprise:

a fourth frequency divider configured to generate a fourth divided signal by dividing the output signal by a second division factor equal to the common multiplier;

a third selection stage configured to provide an intermediate signal as a selected one of the output signal and the fourth divided signal, wherein the controller is configured to control the third selection stage to select the output signal in the initial and final modes and to select the fourth divided signal in the interim mode; and

a fifth frequency divider configured to generate the first comparison signal by dividing the intermediate signal by a first division factor dependent, in the initial mode, on the initial frequency and, in the interim and final modes, on the final frequency.

Likewise, in the method, generating the first comparison signal may comprise: generating a fourth divided signal by dividing the output signal by a second division factor equal to the common multiplier;

providing an intermediate signal as a selected one of the output signal and the fourth divided signal, wherein in the initial and final modes the output signal is selected, and in the interim mode the fourth divided signal is selected; and generating the first comparison signal by dividing the intermediate signal by a first division factor dependent, in the initial mode, on the initial frequency and, in the interim and final modes, on the final frequency.

These features enable low power consumption by enabling the dividing of the output signal by the second division factor to be suspended during the initial and final modes.

The second frequency division stage may comprise:

a third frequency divider configured to generate a third divided signal by dividing the reference signal by a/the second division factor equal to the common multiplier; and a second selection stage configured to provide the second comparison signal as a selected one of the reference signal and the third divided signal;

wherein the controller is configured to control the second selection stage to select the reference signal in the initial and final modes and to select the third divided signal in the interim mode.

Likewise, in the method, generating the second comparison signal may comprise: generating a third divided signal by dividing the reference signal by a/the second division factor equal to the common multiplier; and

providing the second comparison signal as a selected one of the reference signal and the third divided signal, wherein in the initial and final modes the reference signal is selected, and in the interim mode the third divided signal is selected.

These features enable low power consumption by enabling the dividing of the reference signal to be suspended during the initial and final modes.

The controller may be configured to, if the desired change in the output frequency is less than 1 % of the initial frequency, switch the signal generation device from the initial mode to the final mode without passing through the interim mode. Likewise, if the desired change in the output frequency is less than 1 % of the initial frequency, the method may comprise switching the signal generation device from the initial mode to the final mode without passing through the interim mode. These features enable power consumption and settling time to be reduced by employing the interim mode only for relatively large changes in output frequency.

The signal generation device may comprise a lock detection stage configured to generate an indication of the variability of the oscillator control signal, and the controller may be configured to adjust a duration of the interim mode dependent on the indication of variability. Likewise, the method may comprise generating an indication of the variability of the oscillator control signal and adjusting a duration of the interim mode dependent on the indication of variability. These features enable power consumption and settling time to be reduced by enabling the interim mode to be terminated as soon as the signal generation device is generating the final frequency.

There is also provided a wireless communication device comprising a signal generation device according to the first aspect.

Preferred embodiments are described, by way of example only, with reference to the accompanying drawings.

Brief Description of the Drawings Figure 1 is a diagram of a signal generation device.

Figure 2 is a flow chart illustrating a method of operating a signal generation device.

Figure 3 is a timing diagram.

Figure 4 is a diagram of a signal generation device.

Figure 5 is a diagram of a lock detection stage.

Figure 6 is a diagram of a signal generation device.

Figure 7 is a diagram of a signal generation device.

Figure 8 is a graph illustrating the oscillator control signal as a function of time for a step down in frequency.

Figure 9 is a graph illustrating the oscillator control signal as a function of time for a step up in frequency.

Figure 10 is a graph illustrating the oscillator control signal as a function of time with a fractional divider.

Figure 1 1 is a block diagram of a wireless communication device comprising an oscillator circuit.

Detailed Description of Preferred Embodiments

Referring to Figure 1 , a signal generation device 10 comprises a variable frequency oscillator 100 that generates an output signal Sout having an output frequency Fout dependent on an oscillator control signal Sosc applied at an input 1 10 of the variable frequency oscillator 100. The variable frequency oscillator 100 may be, for example, a voltage controlled oscillator (VCO), in which case the oscillator control signal Sosc is a variable voltage. An output 120 of the variable frequency oscillator 100 is coupled to an input 210 of a first frequency division stage 200 that generates, at an output 220 of the first frequency division stage 200, a first comparison signal Scompl having a first comparison frequency F1 equal to the output frequency Fout divided by a first divisor D1 , by applying frequency division to the output signal Sout. The first divisor D1 is variable, having a value not less than unity. The output 220 of the first frequency division stage 200 is coupled to a first input 310 of a comparator 300.

The signal generation device 10 further comprises a second frequency division stage 400 that generates, at an output 420 of the second frequency division stage 400, a second comparison signal Scomp2 having a second comparison frequency F2 equal to the frequency of a reference signal divided by a second divisor D2, by applying frequency division to a reference signal Sref provided at an input 410 of the second frequency division stage 400. The second divisor D2 is variable, having a value not less than unity. The output 420 of the second frequency division stage 400 is coupled to a second input 320 of the comparator 300.

The comparator 300 generates, at an output 330 of the comparator 300, a difference signal Sdiff dependent on the phase difference between the first and second comparison signals Scompl , Scomp2. Therefore, the difference signal Sdiff is indicative of the phase difference between the first and second comparison signals Scompl , Scomp2. The output 330 of the comparator 300 is coupled to an input 510 of a charge pump 500. The charge pump 500 generates, at an output 520 of the charge pump 500, a current Idiff, which is a pulsed signal, dependent on the difference signal Sdiff. The charge pump 500 has a gain that is variable.

The output 520 of the charge pump 500 is coupled to an input 610 of a filter 600, which may be a low pass filter. The filter 600 generates, at an output 620 of the filter 600, the oscillator control signal Sosc by filtering the current Idiff, and the output 620 of the filter 600 is coupled to the input 1 10 of the variable frequency oscillator 100 for controlling the output frequency Fout of the output signal Sout generated by the variable frequency oscillator 100. The elements of the signal generation device 10, therefore, constitute a phase locked loop.

A controller 700 has an input 710 for an indication AF of a desired change in the output frequency Fout of the output signal Sout. In response to the indication AF, the controller generates, at an output 720 of the controller 700, a mode control signal Smode whereby the signal generation device 10 is switched from an initial mode, in which the output frequency Fout of the output signal Sout has an initial frequency Finitial, to an interim mode for a period of time as described below, and then switched to a final mode, in which the output frequency Fout has a final frequency Ffinal. During the interim mode the output frequency Fout makes a transition from the initial frequency Finitial to the final frequency Ffinal. Therefore, the mode control signal Smode is indicative of when the signal generation device 10 is required to switch from the initial mode to the interim mode, and from the interim mode to the final mode. The output 720 of the controller 700 is coupled to a control input 230 of the first frequency division stage 200 for varying the first divisor D1 in response to the mode control signal Smode, and likewise, the output 720 of the controller 700 is coupled to a control input 430 of the second frequency division stage 400 for varying the second divisor D2 in response to the mode control signal Smode, such that in the interim mode the first and second divisors D1 , D2 are higher than in the final mode by a common multiplier. Similarly, the output 720 of the controller 700 is coupled to a control input 530 of the charge pump 500 for varying the gain of the charge pump 500 in response to the mode control signal Smode, such that in the interim mode the gain is higher than in the final mode. Typically, the gain in the final mode may be equal to the gain in the initial mode.

For optimum performance improvement, the gain of the charge pump 500 in the interim mode is higher than in the final mode by a gain factor equal to the common multiplier. For example, if the common multiplier is two, in which case the first and second divisors D1 , D2 are doubled in the interim mode relative to their values in the final mode, the gain factor is two and so the gain of the charge pump 500 is doubled in the interim mode relative to its value in the final mode. As another example, if the common multiplier is four, in which case the first and second divisors D1 , D2 are quadrupled in the interim mode relative to their values in the final mode, the gain factor is four and so the gain of the charge pump 500 is quadrupled in the interim mode relative to its value in the final mode.

Some improvement in performance may nevertheless be obtained despite the gain factor and the common multiplier being unequal. Preferably, the gain factor is equal to the common multiplier within twenty percent, ten percent, or five percent, or two percent, or one percent. For example, if the common multiplier is two, and the gain factor is equal to the common multiplier within ten percent, the gain of the charge pump 500 is increased to a value in the range 1.8 to 2.2 times its value in the final mode.

Operation of the signal generation device 10 is described below with reference to the flow chart of Figure 2 and the timing diagram of Figure 3. Initially, at time to, the mode control signal Smode has an initial state, and the signal generation device 10 is operating in the initial mode, as indicated at step 800. In this initial mode, the first and second divisors D1 , D2 and the gain of the charge pump 500 each have respective initial values. In particular, the initial value of the first divisor D1 will typically depend on the initial frequency Finitial of the output frequency Fout. At step 802, the controller 700 receives, at time t1 , the indication F of a desired change in the output frequency Fout of the output signal Sout, or equivalently a desired final frequency Ffinal of the output frequency Fout. ln the example illustrated in Figure 3, the final frequency Ffinal is higher than the initial frequency Finitial, but in other examples it may be lower. At step 804 the controller 700 determines the required final values of the first and second divisors D1 , D2 for generating the final frequency Ffinal. In order to generate the higher final frequency Ffinal illustrated in Figure 3, the first divisor D1 has a value higher than for generating the initial frequency Finitial. Typically, the required final value of the second divisor D2 may be the same as its initial value.

At step 806, in response to the indication AF, the controller 700 switches, at time t2, the mode control signal Smode from the initial state to an interim state, and in response to the interim state of the mode control signal Smode, the first frequency division stage 200 switches the first divisor D1 from its initial value to an interim value determined as the required final value of the first divisor D1 scaled up by the common multiplier. Likewise, at step 806, in response to the interim state of the mode control signal Smode, the second frequency division stage 400 switches the second divisor D2 from its initial value to an interim value determined as the required final value of the second divisor D2 scaled up by the common multiplier. Furthermore, at step 806, in response to the interim state of the mode control signal Smode, the charge pump 500 increases its gain to a higher, interim value. Time t2 is, therefore, the commencement of the interim mode of operation of the signal generation device 10.

At step 808, controller 700 switches, at time t3, the mode control signal Smode from the interim state to a final state, which may be the same as the initial state. Also at step 808, in response to the final state of the mode control signal Smode, the first frequency division stage 200 switches the first divisor D1 to its required final value, the second frequency division stage 400 switches the second divisor D2 to its required final value, and the charge pump 500 decreases its gain back to its initial value. Time t3 is the end of the interim mode of operation of the signal generation device 10 and the commencement of the final mode of operation. During the interim mode of operation of the signal generation device 10, the output frequency Fout of the variable frequency oscillator 100 changes from the initial frequency Finitial to the final frequency Ffinal, as illustrated in Figure 3, although the change with time is not necessarily linear.

The period between time t2 and t3, that is, the duration of the interim mode may be fixed, that is, constant. In other embodiments, this period may be variable, for example dependent on the frequency Fout of the variable frequency oscillator 100, and/or dependent on the indication AF of the desired change in the frequency Fout. In the latter case, the duration of the interim mode may be determined by the controller 700. Figure 4 illustrates a signal generation device 12 in which the duration of the interim mode is variable. Elements of the embodiment illustrated in Figure 4 that are identical to elements of the embodiment of Figure 1 have corresponding reference numerals and are not described again. Only the differences are described. Referring to Figure 4, the signal generation device 12 comprises a lock detection stage 900 having an input 902 coupled to the output 620 of the filter 600 for receiving the oscillation control signal Sosc, and an output 904 coupled to an input 730 of the controller 700. The lock detection stage 900 generates, at the output 904 of the lock detection stage 900, an indication Slock of the variability of the oscillator control signal Sosc, and the controller 700 determines the duration of the interim mode dependent on the indication Slock.

Typically, the controller 700 may maintain the interim mode until the variability of the oscillator control signal Sosc is less than a threshold, indicating that the phase locked loop of the signal generation device 12 has locked onto the final frequency Ffinal. The lock detection stage 900 may, for example, determine the peak-to-peak variation of the oscillator control signal Sosc measured over a period of time, compare the peak-to-peak variation with a threshold, and set the value of the indication Slock dependent on whether the peak-to-peak variation is above or below the threshold.

Figure 5 illustrates an embodiment of the lock detection stage 900. Referring to Figure 5, the lock detection stage 900 comprises an analogue-to-digital converter (A/D) 910 having an input 912 coupled to the input 902 of the lock detection stage 900 for receiving the oscillator control signal Sosc. The A/D 910 converts the oscillator control signal Sosc to a first binary signal that is delivered at an output 914 of the A/D 910. The output 914 of the A/D 910 is coupled to an input 922 of a delay stage 920 and to a first input 932 of a first comparator 930. The delay stage 920 delivers, at an output 924 of the delay stage 920, a delayed version of the first binary signal. The output 924 of the delay stage 920 is coupled to a second input 934 of the first comparator 930. The first comparator 930 delivers, at an output 936 of the first comparator 930, a second binary signal comprising pulses, wherein a pulse is generated when the first binary signal and the delayed version of the first binary signal differ, and therefore the number of pulses in the second binary signal is indicative of the variability of the oscillator control signal Sosc. The output 936 of the first comparator 930 is coupled to an input 942 of a counter 940 that counts the pulses in the second binary signal and delivers at an output 944 of the counter 940 an indication of the count value. The output 944 of the counter is coupled to a first input 952 of a second comparator 950. A threshold value THR is provided to the second comparator 950 at a second input 954 of the second comparator 950. The second comparator 950 generates, at an output 956 of the second comparator 950, the indication Slock, whereby a count value delivered by the counter 940 exceeding the threshold THR indicates a relatively high variability, and high peak-to-peak variation, of the oscillator control signal Sosc, corresponding to the signal generation device 12 being out of lock, or more specifically the first comparison signal Scompl not being synchronised with the second comparison signal Scomp2. Conversely, a count value below the threshold THR indicates a relatively low variability, and low peak-to-peak variation, of the oscillator control signal Sosc, corresponding to the signal generation device 12 being in lock, or more specifically the first comparison signal Scompl being synchronised with the second comparison signal Scomp2. The first A/D 910, the delay 920, the first comparator 930, and the counter 940 may be clocked by a common clock, for example the reference signal Sref, or the first or second comparison signals Scompl , Scomp2. The counter 940 may be reset every Nlockdet clock cycles, where Nlockdet represents a window size over which the oscillator control signal Sosc is assessed, for example 32 clock cycles, and the second comparator 950 may be clocked to take decisions just before the counter 940 is reset.

In some embodiments, the switching of the mode control signal Smode to its interim state by the controller 700, and therefore the switching from the initial mode to the interim mode, may be conditional on the desired change F in the frequency Fout of the output signal Sout exceeding a specific proportion, for example 1 %, of the frequency of the output signal Sout. In this case, for relatively small values of F less than this specific proportion, the signal generation device 10 may change directly from the initial mode to the final mode without passing through the interim mode.

Figure 6 illustrates in more detail a signal generation device 14 which is an embodiment of the signal generation device 10 described above, also illustrating embodiments of the first frequency division stage 200, the second frequency division stage 400, the comparator 300, the charge pump 500 and the filter 600, each of which are described below.

Referring to Figure 6, the first frequency division stage 200 comprises a first frequency divider 240 configured to generate a first divided signal Sdivl by dividing the output signal Sout by a first division factor N1 and a second frequency divider 250 configured to generate a second divided signal Sdiv2 by dividing the first divided signal Sdivl by a second division factor N2. Therefore, the first divisor D1 is equal to the product of the first and second division factors N1 , N2, that is, D1 =N1xN2.

In more detail, the first frequency division stage 200 comprises the first frequency divider 240 having a signal input 241 coupled to the input 210 of the first frequency division stage 200 for receiving the output signal Sout, and a division factor input 243 for receiving the first division factor N1. The first frequency divider 240 generates the first divided signal Sdivl at an output 242 of the first frequency divider 240 by dividing the output signal Sout by the first division factor N1. Therefore, the first divided signal Sdivl corresponds to the output signal Sout divided by the first division factor N1.

The second frequency divider 250 has a signal input 251 coupled to the output 242 of the first frequency divider 240 for receiving the first divided signal Sdivl , and a division factor input 253 for receiving the second division factor N2. The second frequency divider 250 divides the first divided signal Sdivl by the second division factor N2. An output 252 of the second frequency divider 250 is coupled to a first input 261 of a first selection stage 260, which may be a multiplexer (MUX). The signal input 251 of the second frequency divider 250 is coupled to a second input 262 of the first selection stage 260. A control input 264 of the first selection stage 260 is coupled to the output 720 of the controller 700 for receiving the mode control signal Smode. In response to the mode control signal Smode having the initial and final state, the second input 262 of the first selection stage 260 is coupled to an output 263 of the first selection stage 260, thereby delivering the first divided signal Sdivl at the output 263. In response to the mode control signal Smode having the interim state, the first input 261 of the first selection stage 260 is coupled to the output 263 of the first selection stage 260, thereby by delivering the second divided signal Sdiv2 at the output 263. The output 263 of the first selection stage 260 is coupled to the output 220 of the first frequency division stage 200 for delivering the first comparison signal Scompl . Therefore, in response to the mode control signal Smode having the initial and final state, the first comparison signal Scompl corresponds to the first divided signal Sdivl , that is, the output signal Sout divided by the first division factor N1 , and in response to the mode control signal Smode having the interim state, the first comparison signal Scompl corresponds to the first divided signal Sdivl divided by the second division factor N2, that is, the output signal Sout divided by both the first division factor N1 and the second division factor N2. Therefore, the first divisor D1 is variable, taking the value of the first division factor N1 or of the higher value corresponding to the product of the first and second division factors N1 , N2, dependent on the mode control signal Smode.

Moreover, the first division factor N1 is variable, for example under the control of the controller 700, dependent on the required output frequency Fout.

Continuing to refer to Figure 6, the second frequency division stage 400 comprises a third frequency divider 430 having a signal input 431 coupled to the input 410 of the second frequency division stage 400 for receiving the reference signal Sref, and a division factor input 432 for receiving the second division factor N2. The third frequency divider 430 generates a third divided signal Sdiv3 at an output 433 of the third frequency divider 400 by dividing the reference signal Sref by the second division factor N2. The output 433 of the third frequency divider 430 is coupled to a first input 441 of a second selection stage 440, which may be a multiplexer. The signal input 431 of the third frequency divider 430 is coupled to a second input 442 of the second selection stage 440. A control input 444 of the second selection stage 440 is coupled to the output 720 of the controller 700 for receiving the mode control signal Smode. In response to the mode control signal Smode having the initial or final state, the second input 442 of the second selection stage 440 is coupled to an output 443 of the second selection stage 440, thereby delivering the reference signal Sref at the output 443. In response to the mode control signal Smode having the interim state, the first input 441 of the second selection stage 440 is coupled to the output 443 of the of the second selection stage 440 thereby delivering at the output 443 the third divided signal Sdiv3 resulting from the division of the reference signal Sref by the second division factor N2. The output 443 of the second selection stage 440 is coupled to the output 420 of the second frequency division stage 400 for delivering the second comparison signal Scomp2. Therefore, in response to the mode control signal

Smode having the initial or final state, the second comparison signal Scomp2 corresponds to the reference signal Sref, and in response to the mode control signal Smode having the interim state, the second comparison signal Scomp2 corresponds to the reference signal Sref divided by the second division factor N2.

In the embodiment of the signal generation device 14 illustrated in Figure 6, in the interim mode the output signal Sout is divided in the first frequency division stage 200 first by the first division factor N1 and then by the second division factor N2. Alternatively, the order of division may be swapped, such that the output signal Sout is divided first by the second division factor N2 and then by the first division factor N1 . Such an alternative embodiment is illustrated in Figure 7. The signal generation device 16 illustrated in Figure 7 is identical to the signal generation device 14 of Figure 6, except for a different embodiment of the first frequency division stage 200, which is described below.

Referring to Figure 7, first frequency division stage 200 comprises a fourth frequency divider 290 having a signal input 291 coupled to the input 210 of the first frequency division stage 200 for receiving the output signal Sout, and a division factor input 293 for receiving the second division factor N2. The fourth frequency divider 290 divides the output signal Sout by the second division factor N2, thereby generating a fourth divided signal Sdiv4 that is delivered at an output 292 of the fourth frequency divider 290. The output 292 of the fourth frequency divider 290 is coupled to a first input 271 of a third selection stage 270, which may be a multiplexer. The signal input 291 of the fourth frequency divider 290 is coupled to a second input 272 of the third selection stage 270. The third selection stage 270 delivers an intermediate signal Sint at an output 273 of the third selection stage 270. A control input 274 of the third selection stage 270 is coupled to the output 720 of the controller 700 for receiving the mode control signal Smode. In response to the mode control signal Smode having the initial and final state, the second input 272 of the third selection stage 270 is coupled to the output 273 of the third selection stage 270 whereby the intermediate signal Sint corresponds to the output signal Sout. In response to the mode control signal Smode having the interim state, the first input 271 of the third selection stage 270 is coupled to the output 273 of the third selection stage 270, whereby the intermediate signal Sint corresponds to the fourth divided signal Sdiv4. The output 273 of the fourth selection stage 270 is coupled to a signal input 281 of a fifth frequency divider 280. The fifth frequency divider 280 has a division factor input 283 for receiving the first division factor N1 . The fifth frequency divider 280 divides the intermediate signal Sint by the first division factor N1 , thereby generating the first comparison signal Scompi at an output 282 of the fifth frequency divider 280 that is coupled to the output 220 of the first frequency division stage 200.

Therefore, in response to the mode control signal Smode having the initial and final state, the first comparison signal Scompi corresponds to output signal Sout divided by the first division factor N1 , and in response to the mode control signal Smode having the interim state, the first comparison signal Scompi corresponds to the output signal Sout divided by both the first division factor N1 and the second division factor N2. Therefore, the first divisor D1 is variable, taking the value of the first division factor N1 or of the higher value corresponding to the product of the first and second division factors N1 , N2, dependent on the mode control signal Smode. Moreover, the first division factor N1 is variable, for example under the control of the controller 700, dependent on the required output frequency Fout.

Referring again to Figure 6, the comparator 300 comprises a first flip-flop 350 and a second flip-flop 360. The first flip-flop 350 has a first input 352 coupled to a first voltage rail 40, and a second input 351 coupled to the second input 320 of the comparator 300 for receiving the second comparison signal Scomp2. The second flip-flop 360 has a first input 362 coupled to the first voltage rail 40, and a second input 361 coupled to the first input 310 of the comparator 300 for receiving the first comparison signal Scompi . The output 330 of the comparator 300 has two output ports; a first output port 330A for delivering a first signal portion, referenced SdiffA, of the difference signal Sdiff, and a second output port 330B for delivering a second signal portion, referenced SdiffB, of the difference signal Sdiff. The first signal portion SdiffA provides pulses for increasing the charge in the loop filter 600 using the charge pump 500, and the second signal portion SdiffB provides pulses for decreasing the charge in the loop filter 600 using the charge pump 500. An output 353 of the first flip-flop 350 is coupled to the first output port 330A for delivering the first signal portion SdiffA, and an output 363 of the second flip-flop 360 is coupled to the second output port 330B for delivering the second signal portion SdiffB. The output 353 and output 363 are also coupled to respective inputs of an AND gate 370, and an output of the AND gate 370 is coupled to a third input of each of the first and second flip-flops 350, 360 via an inverter 380. Alternatively, the combination of the AND gate 370 and the inverter 380 may be replaced by a NAND gate.

Continuing to refer to Figure 6, the charge pump 500 comprises a first charge pump stage CP1 and a second charge pump stage CP2. The input 510 of the charge pump 500 has two input ports; a first input port 51 OA for receiving the first signal portion SdiffA for increasing the charge in the loop filter 600 using the charge pump 500, and a second input port 510B for receiving the second signal portion SdiffB for decreasing the charge in the loop filter using the charge pump 500. The first charge pump stage CP1 comprises a first current source 11 coupled in series with first and second switches X1 , X2, between the first voltage rail 40 and the output 520 of the charge pump 500, a second current source I2 coupled in series with third and fourth switches X3, X4, between a second voltage rail 30 and the output 520, a third current source I3 coupled in series with fifth and sixth switches X5, X6, between the first voltage rail 40 and the output 520, and a fourth current source I4 coupled in series with a seventh and eighth switches X7, X8, between the second voltage rail 30 and the output 520. The first and second current sources 11 , I2 are arranged to deliver a current Ip when the first and second switches X1 , X2 or the third and fourth switches X3, X4 are in a conducting state, and the third and fourth current sources I3, I4 are arranged to deliver a current lpxN3, that is, N3 times larger than Ip, when the fifth and sixth switches X5, X6 or the seventh and eighth switches X7, X8 are in a conducting state. The second and sixth switches X2, X6 are opened and closed in response to the first signal portion SdiffA, being closed, that is, conducting, when the charge in the loop filter 600 is to be increased by the charge pump 500, and otherwise open, that is, non-conducting. The third and seventh switches X3, X7 are opened and closed in response to the second signal portion SdiffB, being closed when the charge in the loop filter is to be reduced by the charge pump 500, and open otherwise. The first, fourth, fifth and eighth switches X1 , X4, X5, X8 are controlled by the controller 700, opening and closing, respectively, to deactivate and activate the first and second charge pump stages CP1 , CP2 in response to the mode control signal Smode delivered via the control input 530 of the charge pump 500. The first and second charge pump stages

CP1 , CP2, therefore, when enabled, each generate a pulsed signal comprising pulses of current having a magnitude of Ip or lpxN3 respectively, and a pulse duration and polarity dependent on the a first and second signal portions SdiffA.SdiffB of the difference signal.

Two alternative schemes of opening and closing the first, fourth, fifth and eighth switches X1 , X4, X5, X8 are possible, in brief, according to whether the first charge pump stage CP1 delivers current only during the initial and final modes, or also during the interim mode. In both modes the second charge pump stage CP2 delivers current only during the interim mode.

In the first scheme, the first and fourth switches X1 , X4 are closed, that is, conducting, when the mode control signal Smode has the initial and final state, thereby enabling the first charge pump stage CP1 to generate the pulses of current of magnitude Ip during the initial and final modes, and open, that is, non-conducting, when the mode control signal Smode has the interim state, so disabling the first charge pump stage CP1 from generating current during the interim mode. Conversely in the first scheme, the fifth and eighth switches X5, X8 are open when the mode control signal Smode has the initial and final state, thereby disabling the second charge pump stage CP2 from generating current during the initial and final modes, and closed when the mode control signal Smode has the interim state, thereby enabling the second charge pump stage CP2 to generate the pulses of current of magnitude lpxN3 during the interim mode. In the first scheme, therefore, the current generated by the charge pump 500 in the interim mode is N3 times larger than the current it generates in the initial and final modes. Therefore, the gain of the charge pump 500 is increased by multiplication by a gain factor. In this example, the gain factor is preferably equal to the common multiplier described above, and more particularly is equal, in the embodiments described with reference to Figures 6 and 7, to the second division factor N2. This is achieved be setting N3=N2. More generally, the gain factor may differ from the common multiplier, but preferably within the limits described above, and is the amount by which the gain of the charge pump 500 is multiplied for the duration of the interim mode.

In the second scheme, the first and fourth switches X1 , X4 may be closed, that is, conducting, when the mode control signal Smode has the initial, interim and final state, thereby enabling the first charge pump stage CP1 to generate the pulses of current of magnitude Ip throughout the initial, interim and final modes, and the fifth and eighth switches X5, X8 may be open when the mode control signal Smode has the initial and final state, thereby disabling the second charge pump stage CP2 from generating current during the initial and final modes, and closed when the mode control signal Smode has the interim state, thereby enabling the second charge pump stage CP2 to generate the pulses of current of magnitude lpxN3 during the interim mode. In the second scheme, therefore, the current generated by the charge pump 500 in the interim mode is (1 +N3) times larger than the current it generates in the initial and final modes, being the sum of the currents generated by the first and second charge pump stages CP1 , CP2. In this scheme, to make the charge pump gain factor in the interim mode equal to the common multiplier, N3 should be equal to N2-1. If only using this second scheme it is possible to simplify the charge pump 500 by eliminating the switches X1 and X4, since these are then always on.

Continuing to refer to Figure 6, the filter 600 comprises its input 610 and its output 620 coupled together, a first capacitive device C1 coupled between the input 610 and the second voltage rail 30, and a resistive element R and a second capacitive element C2 coupled in series between the input 610 and the second voltage rail 30. The first and second capacitive elements C1 , C2 are charged and discharged by the pulses of current of the pulsed signal generated by the charge pump 500, thereby generating the oscillator control signal Sosc as a voltage at the output 620 of the filter 600.

Figure 8 is a graph illustrating the oscillator control signal Sosc as a function of time for a step down in the output frequency Fout from 61.596GHz to 58.5GHz. Curve B corresponds to the signal generation device 10 in which the first and second divisors D1 , D2 and the gain are changed during the interim mode as described herein, in this example the first divisor being higher during the interim mode than in the final mode by a common multiplier of eight times, the second divisor D2 being increased during the interim mode by the common multiplier of eight times, and the gain being increase during the interim mode by a gain factor of eight times. Curve A illustrates the oscillator control signal Sosc if the first divisor D1 is switched directly to its final value without passing through the interim mode, and the second divisor D2 and the gain are unchanged throughout the change from the initial frequency Finitial to the final frequency Ffinal. It can be seen that employing the interim mode as described herein reduces the settling time of the signal generation device 10 from about 3.8μ8 to about 0.7μ8.

Figure 9 is a graph illustrating the oscillator control signal Sosc as a function of time for a step up in the output frequency Fout from 58.248GHz to 60.192GHz. Again, curve B corresponds to the scheme described herein, with a common multiplier of eight times and a gain factor of eight times, and curve A illustrates the oscillator control signal Sosc if the first divisor D1 is switched directly to its final value without passing through the interim mode, and the second divisor D2 and the gain are unchanged throughout the change from the initial frequency Finitial to the final frequency Ffinal. It can be seen that employing the interim mode as described herein reduces the settling time of the signal generation device 10 from about 4.8μ8 to 1.2μ8. The first and second division factors N1 , N2 may be integers, but alternatively fractional division factors, that is, fractional division ratios, may be employed. Figure 10 is a graph illustrating the oscillator control signal Sosc as a function of time for a step down in the output frequency Fout to 59.132GHz when the first frequency divider 240 is a fractional divider, providing fractional division. Comparing curves A and B in Figure 10, which represent settling times with and without the interim mode described herein, it can be seen that employing the interim mode as described herein reduces the settling time of the signal generation device 10 from about 5.8 s to about 1 .θμβ. A similar improvement has also been found when commencing the frequency change with different division ratios in the initial mode.

Referring to Figure 1 1 , a wireless communication device 960 comprises a transceiver (Tx/Rx) 961 coupled to an antenna 962 for transmitting and receiving radio frequency (RF) signals, and coupled to a digital signal processor (DSP) 963 that processes baseband signals that are received or are to be transmitted at RF. The wireless communication device 960 also comprises the signal generation device 10 coupled to the transceiver 961 . The transceiver 961 generates quadrature local oscillator signals from the output signal Sout delivered by the signal generation device 10 at the output 120 of the variable frequency oscillator 100. The DSP 963 is coupled to the input 710 of the controller 700 for supplying to the signal generation device 10 the indication F of the desired change in the output frequency Fout of the output signal Sout.

Features that are described in the context of separate embodiments may be provided in combination in a single embodiment. Conversely, features that are described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.

It should be noted that the term "comprising" does not exclude other elements or steps, the term "a" or "an" does not exclude a plurality, a single feature may fulfil the functions of several features recited in the claims and reference signs in the claims shall not be construed as limiting the scope of the claims. It should also be noted that where a component is described as being "configured to", "arranged to" or "adapted to" perform a particular function, it may be appropriate to consider the component as merely suitable "for" performing the function, depending on the context in which the component is being considered. Throughout the text, these terms are generally considered as

interchangeable, unless the particular context dictates otherwise. It should also be noted that the Figures are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the present invention.