Signal processor comprising an integrating analog-to-digital converter

FIELD OF THE INVENTION

An aspect of the invention relates to a signal processor that comprises an integrating analog-to-digital converter. The integrating analog-to-digital converter may be implemented in the form of, for example, an integrated circuit, which may comprise other functional entities of the signal processor. Other aspects of the invention relate to a method of analog-to-digital conversion, a measurement system, and a computer program product for a programmable processor.

BACKGROUND ART An integrating analog-to-digital converter can provide a digital value on the basis of a conversion cycle in which a capacitance is charged and discharged by means of a signal-representing current and at least one reference current. Such an integrating analog-to- digital converter is often referred to as dual-slope or multi-slope converter. The signal- representing current may charge the capacitance, which produces a positive voltage slope, whereas a reference current may discharge the capacitance, which produces a negative voltage slope, or vice versa.

A dual-slope converter, which employs a single reference current, typically operates as follows. The capacitance has a start voltage at the start of a conversion cycle. The signal-representing current charges or discharges the capacitance for a given duration. Subsequently, the reference current discharges or charges, respectively, the capacitance until the start voltage is reached. The reference current needs to be applied to the capacitance for a particular duration in order to bring the capacitance back to the start voltage. A counter measures this particular duration in terms of number of clock cycles. The number of clock cycles that the counter has counted, constitutes a digital value that represents an input signal value.

US patent 7,064,694 discloses a multi-cycle, multi-slope analog-to-digital converter. In this analog-to-digital converter, charge and discharge periods overlap in order to reduce latency. Additionally, charging and discharging of an integration capacitor during a measurement cycle occurs between defined thresholds so as to avoid saturation within the

analog-to-digital converter. To that end, the analog-to-digital converter comprises various comparators, including a comparator that receives a lower threshold voltage and another comparator that receives a higher threshold voltage.

SUMMARY OF THE INVENTION

It is an object of the invention to provide an analog-to-digital conversion technique that allows relatively low-cost implementations, in particular low-cost integrated circuit implementations. The independent claims define various aspects of the invention. The dependent claims define additional features for implementing the invention to advantage. The invention takes the following points into consideration. In the dual-slope converter described hereinbefore, the capacitance has a voltage that will remain within a given range when the signal-representing current is applied to the capacitance during a time interval of given length. The signal-representing current has a steepest slope when a maximum input signal value occurs. The given range, within which the voltage of the capacitance will remain, is equal to the steepest slope multiplied by the given length of the time interval during which the signal-representing current is applied to the capacitance. Accordingly, saturation can be prevented by defining a sufficiently short time interval during which the signal-representing current is applied to the capacitance. However, such a relatively short time interval requires a relatively high clock frequency in order to achieve a given resolution.

In accordance with the invention, a controller applies a predefined number conversion sub-cycles within the conversion cycle. A conversion sub-cycle comprises a time interval of predefined length during which the signal-representing current is applied to the capacitance, which causes a voltage change. In a subsequent time interval, a reference current Iref is applied to the capacitance so as to substantially compensate the voltage change.

Applying a predefined number conversion sub-cycles within a conversion cycle allows achieving a satisfactory resolution with a relatively low clock frequency. A rounding error, which occurs in a conversion sub-cycle, will be compensated for in a subsequent conversion sub-cycle. Accordingly, saturation can be prevented, without a penalty in terms of resolution, by defining a sufficiently short time interval during which the signal-representing current is applied to the capacitance, while providing a sufficient number of conversion sub-cycles. There is no need for a plurality of comparators that maintain the voltage of the capacitance in a given range as in the prior art. For those reasons, the invention allows relatively low-cost implementations.

A more specific advantage of the invention relates to the following points. A voltage slope, which occurs in an integrating analog-to-digital converter, has a steepness that is typically defined by a so-called RC product: a resistance value multiplied by a capacitance value. The smaller the RC product is, the steeper the voltage slope will be. It is relatively costly to form a relatively large RC product within an integrated circuit. Consequently, an integrating analog-to-digital converter that forms part of an integrated circuit, will exhibit relatively steep voltage slopes, unless external components are used.

In case of a conventional dual-slope converter, as described hereinbefore, relatively steep voltage slopes require a relatively high clock frequency or a relatively high supply voltage, or both, a in order to achieve a given resolution. A relatively high clock frequency generally entails relatively high power consumption and may require relatively expensive manufacturing processes. A relatively high supply voltage is not feasible in particular applications, such as, for example, battery-operated applications.

In contrast, an integrating analog-to-digital converter in accordance with the invention can provide sufficient resolution when voltage slopes are relatively steep, while operating at a relatively low clock frequency and at a relatively low supply voltage. This is because the conversion cycle is effectively divided into a predefined number of conversion sub-cycles, whereby a rounding error in a conversion sub-cycle is compensated for a subsequent conversion sub-cycle. Consequently, the invention allows relatively low-cost integrated circuit implementations, which have relatively low power consumption. The invention can be applied to advantage in relatively small products that are battery-operated, such as, for example, handheld products.

An implementation of the invention advantageously comprises one or more of following additional features, which are described in separate paragraphs that correspond with individual dependent claims.

The time interval of predefined length during which the signal-representing current is applied to the capacitance, preferably corresponds with a predefined number of clock cycles in a clock signal.

The controller may alternately activate a signal-representing current source and a reference current source during a conversion cycle. The signal-representing current source applies the signal-representing current to the capacitance when activated; the reference current source applies the reference current to the capacitance when activated.

The reference current preferably has a value that is substantially equal to a maximum value of the signal-representing current.

The controller preferably imposes a reference voltage onto the capacitance by means of a reset switch after a conversion cycle has been completed, and maintains the reference voltage on the capacitance until a subsequent conversion cycle begins.

The analog-to-digital converter preferably comprises a single detector, which detects whether the capacitance has a voltage that is below the reference voltage, or not.

A counter may count the number of clock cycles that occur during the time interval when the reference current is applied to the capacitance.

The same counter is preferably also used for counting the predefined number of clock cycles. A detailed description with reference to drawings illustrates the invention summarized hereinbefore, as well as the additional features.

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 is a block diagram that illustrates a measurement system. Fig. 2 is a functional diagram that illustrates an integrating analog-to-digital converter, which forms part of the measurement system.

Fig. 3 is a signal diagram that illustrates a conversion cycle in the integrating analog-to-digital converter.

Fig. 4 is a flow chart that illustrates a series of steps, which are carried out in the conversion cycle.

Fig. 5 is a signal diagram that illustrates various signals and values occurring during the conversion cycle in the integrating analog-to-digital converter.

DETAILED DESCRIPTION Fig. 1 illustrates a measurement system MSY that comprises a sensor SNS, an analog-to-digital converter ADC, a digital processor DPR, and a display device DPL. The measurement system MSY further comprises a clock generator CKG and a user interface UIF. The measurement system MSY may be, for example, an electronic compass.

The measurement system MSY basically operates as follows. The sensor SNS provides a sensor signal VS that represents a physical quantity, such as, for example, the earth's magnetic field. The sensor signal VS is amplitude continuous, which means that the sensor signal VS may have any value within a range of real values.

The analog-to-digital converter ADC converts the sensor signal VS into a sequence of digital values DV. A digital value DV represents the value that the sensor signal

VS has at a particular instant. The sequence of digital values DV has a rate that depends on a clock signal CK that the clock generator CKG provides. The rate may be relatively low, such as, for example, 1000 digital values per second, which corresponds with a frequency of 1 kHz. The digital processor DPR establishes a measurement result on the basis of one or more digital values DV that the analog-to-digital converter ADC provides. The display device DPL displays the measurement result. To that end, the digital processor DPR applies a display driver signal DD to the display device DPL. The digital processor DPR may be capable of establishing different types of measurement results. Moreover, a measurement result may be displayed in different fashions. A user may select a desired type of measurement result, as well as a desired display mode, by means of the user interface UIF.

Fig. 2 illustrates the analog-to-digital converter ADC, which comprises a capacitive integrator CI. A signal current source SCS and a reference current source RCS are coupled to a capacitive integrator CI. A reset switch RSW and a detector DET are also coupled to the capacitive integrator CI. The analog-to-digital converter ADC further comprises a controller CTRL that includes a counter CNT that provides a count value CV. The capacitive integrator CI typically comprises an integrating capacitance C _int , which may be charged and discharged. The capacitive integrator CI provides an output voltage that varies by charging and discharging the integrating capacitance C _int . For example, the capacitive integrator CI may be implemented so that the integrating capacitance C _int is coupled between an inverting input and an output of an operational amplifier, which also forms part of the capacitive integrator CI. In this implementation, the output voltage may be obtained from the output of the operational amplifier. The output voltage corresponds with a voltage across the integrating capacitance C _int . The output voltage of the capacitive integrator CI will be referred to as integration voltage VI hereinafter.

The signal current source SCS applies a signal current I _slg to the capacitive integrator CI when the signal current source SCS is in an active state, whereas the signal current source SCS does not provide any current in an idle state. The signal current I _slg typically has a value that is proportional to the value of the sensor signal VS. For example, let it be assumed that the sensor signal VS is in the form of a voltage. In that case, the signal current source SCS may be in the form of a transconductance stage, which converts the sensor signal VS into the signal current I _slg .

The reference current source RCS applies a reference current I _re f to the capacitive integrator CI when the reference current source RCS is in an active state, whereas

the reference current source RCS does not provide any current in an idle state. The reference current I _re f has a fixed, predefined value. This fixed, predefined value is preferably equal to a maximum value that the signal current I _slg may have.

In the following, it is assumed that the signal current I _slg charges the integrating capacitance C _int and that the reference current I _re f discharges the integrating capacitance C _int . Consequently, the integration voltage VI increases when the signal current I _slg is applied to the capacitive integrator CI, whereas the integration voltage VI decreases when the reference current I _re f is applied. However, the opposite may apply in an alternative implementation. The integrating capacitance C _int can be completely discharged by bringing the reset switch RSW in a closed state. The integration voltage VI is substantially equal to a reference voltage V _re f when the integrating capacitance C _int has been fully discharged. The reset switch RSW does not affect the integration voltage VI when the reset switch RSW is an open state. The detector DET provides a detection signal DS that indicates whether the integration voltage VI is above the aforementioned reference voltage V _re f, or not. In case the integration voltage VI is equal to the reference voltage V _re f, the integrating capacitance C _int has been completely discharged. In case the integration voltage VI is below the reference voltage V _re f, a residual negative charge is present on the integrating capacitance Cint. In the following, it is assumed that the detection signal DS is in the form of a single bit, which is 1 in the aforementioned cases, and 0 otherwise. That is, 1 indicates a complete discharge. The inverse may apply in an alternative implementation.

The controller CTRL provides various control signals: a charge enable signal EC, a discharge enable signal ED, and a reset signal RS. The charge enable signal EC determines whether the signal current source SCS is an active state or in an idle state. The discharge enable signal ED determines whether the reference current source RCS is an active state or even idle state. The reset signal RS determines whether the reset switch RSW is an open state or a closed state. The controller CTRL provides the aforementioned control signals on the basis of the detection signal DS and the clock signal CK in accordance with a control scheme, which will be described in greater detail hereinafter.

The controller CTRL may be implemented in the form of a suitably programmed processor, which is a software-based implementation. The controller CTRL may also be implemented in the form of a dedicated logic circuit, which is a hardware-based implementation. For example, the controller CTRL may be a state machine, which comprises

one or more flip-flop circuits. A hybrid implementation may comprise a suitably programmed processor, which operates in conjunction with a dedicated logic circuit.

Fig. 3 illustrates an example of a conversion cycle CY on the basis of which the analog-to-digital converter ADC provides a digital value DV. Fig. 3 is a time diagram that comprises a horizontal axis, which represents time, and a vertical axis, which represents the integration voltage VI. The horizontal axis has a vertical position that corresponds with the reference voltage V _re f. The horizontal axis is divided into successive clock cycles CC of the clock signal CK. The conversion cycle CY starts at instant to. Instant ti marks one completed clock cycle after the start at instant to, instant t ₂ marks two completed clock cycles, and so on.

Fig. 3 comprises a curve in full lines that represents the integration voltage VI for a given value of the sensor signal VS. The conversion cycle CY for this given value extends from instant to to instant 133, which instants are indicated on the horizontal axis. A curve in broken lines represents the output value for a maximum value of the sensor signal VS. The maximum value requires a maximum conversion cycle CY _max , which extends from instant to to instant t ₄₈ . In any case, the integrating capacitance C _int contains substantially no charge at instant to. Consequently, the integration voltage VI is substantially equal to the reference voltage V _re f at the start of the conversion cycle CY.

The conversion cycle CY for the given value of the sensor signal VS is as follows. At instant to, the controller CTRL illustrated in Fig. 2 activates the signal current source SCS by means of the charge enable signal EC. Accordingly, the signal current I _slg charges the integrating capacitance C _int . The integration voltage VI increases with a slope that is proportional to the value of the sensor signal VS.

The controller CTRL maintains the signal current source SCS in the active state during a time interval, which has a fixed, predefined length. This time interval will be referred to as first charge period CPl hereinafter. In the example, the first charge period CPl extends from to to t ₁₂ . That is, the fixed, predefined length of the first charge period CPl is 12 clock cycles. At instant t ₁₂ , which marks the end of the first charge period CPl, the integration voltage VI has a value that is proportional to the value of the sensor signal VS. At instant t ₁₂ , the controller CTRL deactivates the signal current source SCS and activates the reference current source RCS by means of the discharge enable signal ED. Accordingly, the reference current I _re f discharges the integrating capacitance C _int . The integration voltage VI decreases with a slope that is proportional to the fixed, predefined value of the reference current I _re f.

Since the integration voltage VI decreases as from instant t ₁₂ , the integration voltage VI will become equal to the reference voltage V _re f at a given instant. This given instant depends on two factors: (1) the value of the integration voltage VI at instant t ₁₂ , which itself depends on the value of the sensor signal VS, and (2) the fixed-predefined value of reference current I _re f. In the example illustrated in Fig. 3, the given instant when the integration voltage VI is equal to the reference voltage V _re f, lies between instant t ₁₆ and instant t ₁₇ .

A time interval extends between the end of the first charge period CPl, which is instant t ₁₂ , and the given instant when the integration voltage VI becomes equal to the reference voltage V _re f. This time interval, which will be referred to as actual first discharge period hereinafter, has a length that is proportional to the value of the sensor signal VS. More specifically, the length of the actual first discharge period is equal to the fixed, predefined length of the first charge time interval, which is 12 clock cycles, multiplied by a ratio between the signal current I _slg and the reference current I _re f whose value is fixed and predefined. The value of the sensor signal VS has effectively been converted into the time domain.

At instant t ₁₇ , the detector DET detects that the integration voltage VI is no longer above the reference voltage V _re f. As a result, the detection signal DS goes from 0 to 1. A time interval extends between the end of the first charge period CPl, which is instant t ₁₂ , and the instant when the detector DET detects that the integration voltage VI is no longer above the reference voltage V _re f, which is instant t ₁₇ . This time interval will be referred to as measured first discharge period DPI hereinafter. The measured first discharge period DPI is expressed as an integer number of clock cycles. The measured first discharge period DPI is 5 clock cycles in this example. The controller CTRL establishes the measured first discharge period DPI by means of the counter CNT illustrated in Fig. 2.

The measured first discharge period DPI is of approximation of the actual first discharge period in terms of number of clock cycles. The actual first discharge period will generally be a non- integer number of clock cycles. Consequently, there is a rounding error, which is a fraction of a clock cycle. For example, referring to Fig. 3, let it be assumed that the actual first discharge period is equal to 4.47 clock periods. The measured first discharge period DPI is a rounding off to the nearest, highest integer, which is 5. The rounding error is equal to 0.53 clock periods.

The rounding error in the measured first discharge period DPI corresponds with a first residual value of the integration voltage VI with respect to the reference voltage

V _re f at instant t ₁₇ . This first residual value, which has a negative sign, is due to the fact that the reference current I _re f has continued to discharge the integrating capacitance C _int after the integration voltage VI became equal to the reference voltage V _re f. There has been a discharge overshoot, as it were. At instant t ₁₇ , the analog-to-digital converter ADC has completed a first conversion sub-cycle SCYl, which comprises the first charge period CPl and the measured first discharge period DPI as described hereinbefore. In principle, the analog-to-digital converter ADC may provide a coarse digital value on the basis of the measured first discharge period DPI, which is 5 clock cycles long. The signal current I _slg has been measured to be equal to 5/12 times the reference current I _re f. That is, the value of the sensor signal VS has been measured to be 5/12 the maximum value of the sensor signal VS. The coarse digital value DV can be expressed as 5 on a scale of 12, 12 representing the maximum value of the sensor signal VS.

The conversion cycle CY illustrated in Fig. 3 comprises a second conversion sub-cycle SCY2, which extends from instant t ₁₇ to instant 1 ₃₃ . The second conversion sub- cycle SCY2 is similar to the first conversion sub-cycle SCYl, which has been described hereinbefore. That is, the second conversion sub-cycle SCY2 comprises a second charge period CP2 and a measured second discharge period DP2, which are similar to the first charge period CPl and the measured first discharge period DPI, respectively. A difference between the first conversion sub-cycle SCYl and the second conversion sub-cycle SCY2, resides in the integration voltage VI, which has a different initial value. In the first conversion sub-cycle SCYl, the integration voltage VI is initially equal to the reference voltage V _re f at instant to, which marks the start of the first conversion sub-cycle SCYl. In the second conversion sub-cycle SCY2, the integration voltage VI is equal to the first residual value, which corresponds with the rounding error in the first conversion sub- cycle SCYl. That is, the second conversion sub-cycle SCY2 takes into account the rounding error in the first conversion sub-cycle SCYl.

In more detail, the second charge period CP2 has a fixed, predefined length of 12 clock cycles, similar to the first charge period CPl. Consequently, the second charge period CP2 extends from instant t ₁₇ to instant t ₂ c _> . In the second charge period CP2, the signal current I _slg charges the integrating capacitance C _int again. The integration voltage VI increases again with a slope that is proportional to the value of the sensor signal VS. The slope is the same as in the first charge period CPl. At instant t ₂ 9, which marks the end of the second charge period CP2, the integration voltage VI will have the value that is somewhat below the

value at instant t ₁₂ , which marks the end of the first charge period CPl. This is due to the first residual value of the integration voltage VI at the end of the first conversion sub-cycle SCYl.

The second measured discharge period DP2 begins at instant t ₂ 9, when the controller CTRL deactivates the signal current source SCS and activates the reference current source RCS by means of the charge enable signal EC and discharge enable signal ED, respectively. In the second measured discharge period DP2, the reference current I _re f discharges the integrating capacitance C _int . The integration voltage VI decreases with a slope that is proportional to the fixed, predefined value of the reference current I _re f. The slope is the same as in the first measured charge period. Since the integration voltage VI decreases as from instant t ₂ 9, the integration voltage VI will again become equal to the reference voltage V _re f at a given instant. This given instant depends on the value of the integration voltage VI at instant t ₂ 9, which itself depends on the value of the sensor signal VS and, in addition, on the first residual value that represents the rounding error in the first conversion sub-cycle SCYl. The given instant further depends on the fixed-predefined value of reference current I _re f. In the example illustrated in Fig. 3, the given instant when the integration voltage VI is equal to the reference voltage V _re f, lies just before instant t33.

An actual second discharge period extends from the second charge period CP2, which is instant t ₂₉ , and the given instant when the integration voltage VI becomes equal to the reference voltage V _re f. The actual second discharge period has a length depends on the value of the sensor signal VS and, in addition, the first residual value that represents the rounding error in the first conversion sub-cycle SCYl. The rounding error, which has a negative sign, effectively shortens the actual second discharge period with respect to the actual first discharge period. This is because the rounding error makes that the actual second discharge period begins with a lower integration voltage VI compared with the actual first discharge period.

At instant t _& , the detector DET detects that the integration voltage VI is no longer above the reference voltage V _re f. This marks the end of the measured second discharge period DP2. The measured second discharge period DP2 is 4 clock cycles in this example. The measured second discharge period DP2 is of approximation of the actual second discharge period in terms of number of clock cycles. Consequently, there will be a rounding error. This rounding error in the measured second discharge period DP2 corresponds with a second residual value of the integration voltage VI with respect to the reference voltage V _re f

at instant t33. In the example illustrated in Fig. 3, the second residual value is small compared with the first residual value.

In the following, it is assumed that the conversion cycle CY is completed when the second conversion sub-cycle SCY2 has been carried out. However, a longer conversion cycle may comprise a third conversion sub-cycle, as well as further conversion sub-cycles.

The controller CTRL establishes the digital value DV when the second conversion sub-cycle SCY2 has been completed. The digital value DV corresponds with a total number of clock cycles that have occurred during the measured first discharge cycle and the measured second discharge cycle. This total number will be referred to as total discharge count hereinafter. In the example illustrated in Fig. 3, the measured first discharge cycle is 5 clock cycles long; the measured second discharge cycle is 4 clock cycles long. The total discharge count is therefore 9 in that case.

The total discharge count is a digital representation of the signal current I _slg with respect to the reference current I _ref . Let it be assumed that the signal current I _slg is equal to the reference current I _re f. This border case corresponds with the curve in broken lines illustrated in Fig. 3. In this border case, the actual first discharge period and the actual second discharge period will each be precisely 12 clock cycles long. Consequently, the total discharge count will be 24, which precisely represents the reference current I _re f without any rounding error. The total discharge count is proportional with the value of the reference current I _re f. Consequently, in case the signal current I _slg is 9/24 times the reference current I _re f, the total discharge count will be 9, which is the case in the example illustrated in Fig. 3.

The digital value, which corresponds with the total discharge count, is a digital representation of the value of the sensor signal VS. This is because the signal current I _slg varies proportionately with the value of the sensor signal VS. Let it be assumed that the signal current I _slg is equal to the reference current I _ref when the value of the sensor signal VS has the maximum value. Let further be assumed that the total discharge count is 24 as in the example. In that case, the total discharge count represents the value of the sensor signal VS on a scale of 24, 24 representing the maximum value. Fig. 4 illustrates a series of steps Sl-SlO, which the controller CTRL carries out in the conversion cycle CY illustrated in Fig. 3. It is assumed that the integrating capacitance C _int is completely discharged when the conversion cycle begins. To that end, the controller CTRL may bring the reset switch RSW in the closed state when a previous conversion cycle has been completed, and maintain the reset switch RSW in the closed state

until the conversion cycle of interest begins. The controller CTRL keeps a current discharge count CDC in addition to the count value CV illustrated in Fig. 2. The controller CTRL further keeps a sub-cycle count SCC.

In step Sl, which marks the beginning of the conversion cycle, the controller CTRL carries out initial operations. The controller CTRL ensures that the reset switch RSW is in the open state (RSW=O). The reset switch RSW remains in the open state until a last conversion sub-cycle has been completed. The controller CTRL sets the current discharge count to 0 (CDC=O). The controller CTRL also sets the sub-cycle count to 0 (SCC=O).

In step S2, which marks the beginning of a conversion sub-cycle, the controller CTRL increments the sub-cycle count by one unit (SCC t+1). The controller CTRL sets the count value CV of the counter CNT to 0 (CV=O). The controller CTRL activates the signal current source SCS by means of the charge enable signal EC (SCS=I). The controller CTRL further ensures that the reference current source RCS is in the idle state by means of the discharge enable signal ED (RCS=O). Accordingly, a charge period commences. In step S3, the counter CNT increments the count value CV by one unit in response to a rising edge in the clock signal CK (CKf => CVt+ 1). A rising edge indicates that one clock cycle has been completed. According, the count value CV represents a number of clock cycles that have elapsed during the charge period.

In step S4, the controller CTRL checks whether the count value CV is equal to a predefined charge period value, or not (CV=CPV?). The predefined charge period value expresses the fixed length of the charge period in terms of number of clock cycles. In the example illustrated in Fig. 3, the predefined charge period value is 12.

In case the count value CV has not yet reached the predefined charge period value, the charge period has not yet been completed. In that case, the controller CTRL carries out step S3 anew. In case the count value CV is equal to the predefined charge period value, the charge period has been completed. In that case, the controller CTRL proceeds by carrying out step S5.

In step S5, which marks the beginning of a discharge period, the controller CTRL deactivates the signal current source SCS and activates the reference current source RCS (SCS=O, RCS=I). The controller CTRL loads the current discharge count into the counter CNT. That is, the count value CV becomes the current discharge count (CV=CDC).

In step S6, the counter CNT increments the current discharge count by one unit in response to a rising edge in the clock signal CK (CKf => CVt+ 1). A rising edge indicates that one clock cycle has been completed. According, the current discharge count

represents a total number of clock cycles within the conversion cycle during which the reference current I _re f has been applied to the capacitive integrator CI.

In step S7, the controller CTRL checks whether the detection signal DS is 1, which indicates that the integration voltage VI is below the reference voltage V _re f, or 0 (DS=I?). In case the detection signal DS is 0, the integrating capacitance C _int has not yet been discharged and the discharge period should continue. In that case, the controller CTRL carries out step S6 anew. In case the detection signal DS is 1, the integrating capacitance C _int has been discharged and the discharge period should terminate. In that case, the controller

CTRL proceeds by carrying out step S8. In step S8, the controller CTRL checks whether the sub-cycle count is equal to a total sub-cycle value, or not (SCC=TSCV?). The total sub-cycle value corresponds with a number of conversion sub-cycles that are comprised within a conversion cycle. In the example illustrated in Fig. 3, the total sub-cycle value is 2.

In case the sub-cycle count has not yet reached the total sub-cycle value, the analog-to-digital converter has not yet carried out all the conversion sub-cycles that are comprised in the conversion cycle. In that case, the controller CTRL carries out step S9 before carrying out a new conversion sub-cycle.

In step S9, the controller CTRL loads the count value CV of the counter CNT, which represents the current discharge count, into a register so that this count is available in the new conversion sub-cycle (CV=CDC→REG). Subsequently, the controller CTRL carries out steps S2-S8 anew, which constitutes the new conversion sub-cycle.

In case the sub-cycle count is equal to the total sub-cycle value, the conversion cycle has been completed. In that case, the controller CTRL proceeds by carrying out step

SlO. In step SlO, the controller CTRL provides the digital value DV on the basis of the current discharge count, which corresponds with the count value CV in the counter CNT

(CDC => DV). At the end of the conversion cycle, the current discharge count corresponds with the total number of clock cycles during which the reference current I _re f has been applied to the capacitive integrator CI. As explained hereinbefore, the current discharge count is a digital representation of the value of the sensor signal VS. The digital value DV may be equal to the current discharge count. Alternatively, the digital value DV may be a scaled version of the current discharge count.

In step SlO, the controller CTRL ensures that the integration voltage VI is equal to the reference voltage V _re f when a subsequent conversion cycle begins. The controller

CTRL does so by bringing the reset switch RSW in a closed state by means of the reset signal RS.

Fig. 5 illustrates various signals within the analog-to-digital converter illustrated in Fig. 2, which occur in the conversion cycle illustrated in Fig. 3. Fig. 5 comprises a horizontal axis, which represents time. Fig. 5 comprises six sections in the form of horizontal bars, which are superposed in a vertical direction. Each particular section represents a particular signal. Going in a vertical direction from top to bottom, the first section represents the clock signal CK. The second section represents the charge enable signal EC. The discharge enable signal ED is the inverse of the charge enable signal EC. The third section represents the integration voltage VI. The fourth section represents the detection signal DS. The fifth section represents the reset signal RS. The sixth section represents the current discharge count CDC.

CONCLUDING REMARKS The detailed description hereinbefore with reference to the drawings is merely an illustration of the invention and the additional features, which are defined in the claims. The invention can be implemented in numerous different manners. In order to illustrate this, some alternatives are briefly indicated.

The invention may be applied to advantage in any type of product or method that relates to analog-to-digital conversion by means of signal integration. The measurement system MSY illustrated in Fig. 1 is merely an example. The invention may equally be applied to advantage in, for example, a communication apparatus that is capable of receiving information via a network, such as, for example, the Internet. The communication apparatus may be in the form of, for example, a personal computer, a set-top box, a cellular phone, or a personal digital assistant.

A conversion cycle may be subdivided in any number of conversion sub- cycles. Fig. 3 illustrates an example in which the conversion cycle CY is subdivided in two conversion sub-cycles only, which is for the sake of simplicity. A conversion cycle may comprise three or more sub-cycles. In this respect, it should also be noted that the time interval of predefined length during which the signal-representing current is applied to the capacitance, may comprise any number of clock cycles. In the example illustrated in Fig. 3, the aforementioned time interval is 12 clock cycles long. As another example, the time interval can be 6 clock cycles long. In that case, the conversion cycle CY illustrated in Fig. 3 can be subdivided in four conversion sub-cycles. As yet another example, the time interval

during which the signal-representing current is applied to the capacitance may comprise only two clock cycles. In that case, discharging the capacitance will either take one clock cycle or two clock cycles. That is, each conversion sub-cycle will produce a binary output in the form of either a single clock cycle count or a dual clock cycle count. This scheme may conceptually be compared with a bit stream converter.

There are numerous manners of implementing an integrating analog-to-digital converter in accordance with the invention. Fig. 2 illustrates an implementation, which comprises a single reference current. A different implementation may comprise a set of reference currents of different magnitude. A controller can account for a reference current of a particular magnitude by assigning a particular weighting factor to a number of clock cycles that have been counted while the reference current was applied to the capacitance. It is also possible to devise an implementation that comprises a set of signal-representing currents of different magnitude. Such an implementation will typically comprise a set of transconductance stages, each of which provides a particular signal-representing current whose magnitude is determined by a conversion gain of the transconductance stage concerned. The controller can use weighting factors to account for different conversion gains.

There are numerous ways of implementing functions by means of items of hardware or software, or both. In this respect, the drawings are very diagrammatic, each representing only one possible embodiment of the invention. Thus, although a drawing shows different functions as different blocks, this by no means excludes that a single item of hardware or software carries out several functions. Nor does it exclude that an assembly of items of hardware or software or both carry out a function.

The remarks made herein before demonstrate that the detailed description with reference to the drawings, illustrate rather than limit the invention. There are numerous alternatives, which fall within the scope of the appended claims. Any reference sign in a claim should not be construed as limiting the claim. The word "comprising" does not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps.